You copied the Doc URL to your clipboard.

ARM Glossary A - E

3A
The combination of Auto White Balance, Auto Exposure, and Autofocus.
A32
The instruction set used by an ARMv8 processor that is in AArch32 execution state. A32 is a fixed-width instruction set that uses 32-bit instruction encoding. It is compatible with the ARMv7 ARM instruction set.
A32 instruction
An instruction executed by a core that is in AArch32 Execution state and A32 Instruction set state. A32 is a fixed-width instruction set that uses 32-bit instruction encodings. Previously, this instruction set was called the ARM instruction set.
A32 state
When a core is in the AArch32 Execution state, if it is in the A32 Instruction set state then it executes A32 instructions.
A64
The instruction set used by an ARMv8 processor that is in AArch64 execution state. A64 is a fixed-width instruction set that uses 32-bit instruction encoding.
A64 instruction
The instruction set used by an ARMv8-A core that is in AArch64 Execution state. A64 is a fixed-width instruction set that uses 32-bit instruction encodings.
AAPCS
The ARM Architecture Procedure Call Standard defines how registers and the stack are used for subroutine calls.
AArch32 state
The ARM 32-bit Execution state that uses 32-bit general purpose registers, and a 32-bit program counter (PC), stack pointer (SP), and link register (LR). AArch32 Execution state provides a choice of two instruction sets, A32 and T32. In implementations of versions of the ARM architecture before ARMv8, and in the ARM R and M architecture profiles, execution is always in AArch32 state.
AArch64 state
The ARM 64-bit Execution state that uses 64-bit general purpose registers, and a 64-bit program counter (PC), stack pointer (SP), and exception link registers (ELR). AArch64 Execution state provides a single instruction set, A64. AArch64 state is supported only in the ARMv8-A architecture profile.
AB
Auto Brightness is an optional feature in Assertive Display which calculates optimal backlight brightness, ignoring internal backlight settings.
ABI
A collection of specifications, some open and some specific to the ARM architecture, that regulate the inter-operation of binary code in a range of execution environments for ARM processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
abort
An abort occurs when an illegal memory access causes an exception. An abort can be generated by the hardware that manages memory accesses, or by the external memory system. The hardware that generates the abort might be a Memory Management Unit (MMU) or a Memory Protection Unit (MPU).
abort model
Describes the changes to the core state when a Data Abort exception occurs. Different abort models behave differently with regard to load and store instructions that specify base register write-back.
ACBC
Assertive Content and Backlight Control is a histogram-based power reduction engine, a constituent part of Assertive Display.
ACE
The AXI Coherency Extensions (ACE) provide additional channels and signaling to an AXI interface to support system level cache coherency.
ACE interface
An AMBA AXI4 interface that includes full support for the ACE protocol. An ACE interface adds:
  • Signals to some of the AXI4 channels.
  • Channels to the AXI4 interface.
ACE protocol
The AXI Coherency Extensions protocol, that adds signals to an AMBA AXI4 interface, to support managing the coherency of a distributed memory system.
ACE-lite interface
An AMBA AXI4 interface that includes support for a subset of the full ACE protocol. An ACE-Lite interface adds signals to some of the AXI4 channels, but does not add any channels to the interface.
ACM
Adaptive Content Management describes the entire video content pipeline of Assertive Display.
AD
Assertive Display is an advanced display management core incorporating backlight and content enhancement and power saving.
adaptive clocking
A technique where the debug interface hardware sends out a clock signal and then waits for the returned clock before generating the next clock pulse. This technique enables the run control unit in the debug hardware to adapt to differing signal drive capabilities and differing cable lengths.
Adaptive Content Management
Adaptive Content Management describes the entire video content pipeline of Assertive Display.
ADC
Assertive Display Control describes the entire backlight pipeline of Assertive Display.
addressing mode
A method of generating the memory address that a load or store instruction uses. The addressing modes mechanism can generate values for data-processing instructions to use as operands. The ADI connects a debugger to a device. The ADI is used to access memory-mapped components in a system, such as processors and CoreSight components.
ADI
The ADI connects a debugger to a device. The ADI is used to access memory-mapped components in a system, such as processors and CoreSight components. The ADI protocol defines the physical wire protocols that are permitted, and the logical programmers model.
Advanced eXtensible Interface
An AMBA bus protocol that supports:
  • Separate phases for address or control and data.
  • Unaligned data transfers using byte strobes.
  • Burst-based transactions with only start address issued.
  • Separate read and write data channels.
  • Issuing multiple outstanding addresses.
  • Out-of-order transaction completion.
  • Optional addition of register stages to meet timing or repropagation requirements.
The AXI protocol includes optional signaling extensions for low-power operation.
Advanced High-performance Bus
An AMBA bus protocol supporting pipelined operation, with the address and data phases occurring during different clock periods. This means that the address phase of a transfer can occur during the data phase of the previous transfer. The AHB provides a subset of the functionality of the AMBA AXI protocol.
advanced Microcontroller Bus Architecture
The AMBA family of protocol specifications is the ARM open standard for on-chip buses. AMBA provides solutions for the interconnection and management of the functional blocks that make up a System-on-Chip (SoC). Applications include the development of embedded systems with one or more processors or signal processors and multiple peripherals.
Advanced Peripheral Bus
An AMBA bus protocol for ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Using the APB to connect to the main system bus through a system-to-peripheral bus bridge can help reduce system power consumption.
Advanced SIMD
A feature of the ARM architecture that provides Single Instruction Multiple Data (SIMD) operations on a dedicated bank of registers. If an implementation also supports scalar floating-point instructions, the Advanced SIMD and floating-point instructions use a common register bank. ARM NEON technology provides the Advanced SIMD instructions, and therefore these are often called the NEON instructions.
Advanced Trace Bus
An AMBA bus protocol for trace data. The ATB is a common bus that is used by the trace components to pass trace data in a system in a data-agnostic format. A trace device can use an ATB to share CoreSight capture resources.
AE
Auto Exposure is the automatic calculation of optimal sensor and lens settings prior to exposure, to control the brightness of an image.
AEL
A version of embedded Linux OS ported to the ARM architecture.
AF
Auto Focus is the automatic calculation and control of lens focus distance, which aims to maximize the sharpness of the image subject.
AG
Analog Gain is the electrical amplification of a signal, before the process of analog-to-digital conversion.
AHB
An AMBA bus protocol supporting pipelined operation, with the address and data phases occurring during different clock periods. This means the address phase of a transfer can occur during the data phase of the previous transfer. The AHB provides a subset of the functionality of the AMBA AXI protocol.
AHB Access Port

An optional component of the DAP that provides an AHB interface to a SoC. CoreSight supports access to a system bus infrastructure using the AHB Access Port (AHB-AP) in the Debug Access Port (DAP).

The AHB-AP provides an AHB master port for direct access to system memory. Other bus protocols can use AHB bridges to map transactions. For example, you can use AHB to AXI bridges to provide AHB access to an AXI bus matrix.

AHB Trace Macrocell
A trace source that makes bus information visible. This information cannot be inferred from the processor using just a trace macrocell. HTM trace can provide:
  • An understanding of multi-layer bus utilization.
  • Software debug. For example, visibility of access to memory areas and data accesses.
  • Bus event detection for trace trigger or filters, and for bus profiling.
AHB-AP

An optional component of the DAP that provides an AHB interface to a SoC. CoreSight supports access to a system bus infrastructure using the AHB Access Port (AHB-AP) in the Debug Access Port (DAP).

The AHB-AP provides an AHB master port for direct access to system memory. Other bus protocols can use AHB bridges to map transactions. For example, you can use AHB to AXI bridges to provide AHB access to an AXI bus matrix.

AHB-Lite
A subset of the full AMBA AHB protocol specification. It provides all of the basic functions required by most AMBA AHB slave and master designs, particularly when used with a multi-layer AMBA interconnect.
AL
Ambient light is defined as being any light in the surroundings of an emissive device that is not emitted by the device.
ALS
An Ambient Light Sensor is a light measurement device often integrated into the front face of a display panel, such as in a mobile device or television.
ambient light
Ambient light is defined as being any light in the surroundings of an emissive device that is not emitted by the device.
Analog Gain
Analog Gain is the electrical amplification of a signal, before the process of analog-to-digital conversion.
APB
An AMBA bus protocol for ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Using the APB to connect to the main system bus through a system-to-peripheral bus bridge can help reduce system power consumption.
APB Access Port

An optional component of the DAP that provides an AHB interface to a SoC. CoreSight supports access to a system bus infrastructure using the AHB Access Port in the Debug Access Port (DAP).

The AHB-AP provides an AHB master port for direct access to system memory. Other bus protocols can use AHB bridges to map transactions. For example, you can use AHB to AXI bridges to provide AHB access to an AXI bus matrix.

APB-AP

An optional component of the DAP that provides an AHB interface to a SoC.

CoreSight supports access to a system bus infrastructure using the AHB Access Port in the Debug Access Port (DAP). The AHB-AP provides an AHB master port for direct access to system memory. Other bus protocols can use AHB bridges to map transactions. For example, you can use AHB to AXI bridges to provide AHB access to an AXI bus matrix.

Application Binary Interface for the ARM Architecture
A collection of specifications, some open and some specific to the ARM architecture, that regulate the inter-operation of binary code in a range of execution environments for ARM processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
Application Processor Status Register
In AArch32 User mode, a restricted form of the CPSR.
APSR
In AArch32 User mode, a restricted form of the CPSR.
architecturally executed
An instruction is architecturally executed only if it would be executed in a simple sequential execution of the program. When such an instruction has been executed and retired it has been architecturally executed. Any instruction that, in a simple sequential execution of a program, is treated as a NOP because it fails its condition code check, and is an architecturally executed instruction. In a processor that performs Speculative execution, an instruction is not architecturally executed if the processor discards the result of the Speculative execution of that instruction.
ARM Compiler for DS-5
ARM Compiler for DS-5 is a suite of tools, together with supporting documentation and examples, that you can use to write and build applications for the ARM family of processors. ARM Compiler for DS-5 supersedes RealView Compilation Tools.
ARM Debug Interface
The ADI connects a debugger to a device. The ADI is used to access memory-mapped components in a system, such as processors and CoreSight components. The ADI protocol defines the physical wire protocols permitted, and the logical programmers model.
ARM Embedded Linux
A version of embedded Linux OS ported to the ARM architecture.
ARM instruction
An instruction executed by a core that is in AArch32 Execution state and A32 Instruction set state. A32 is a fixed-width instruction set that uses 32-bit instruction encodings. Previously, this instruction set was called the ARM instruction set.
ARM profiler
A plug-in to the ARM Workbench Integrated Development Environment that provides non-intrusive analysis of embedded software over time, on targets running at frequencies which are typically as high as 250MHz. Targets can be Real-Time System Models (RTSMs) and hardware targets.
ARM state
When a core is in the AArch32 Execution state, if it is in the A32 Instruction set state then it executes A32 instructions.
ARM TrustZone technology
The hardware and software that enable the integration of enhanced security features throughout a SoC. In ARMv6K, ARMv7-A, and ARMv8-M, the Security Extensions implement the TrustZone hardware. In ARMv8, EL3 incorporates the TrustZone hardware.
ARM Workbench IDE
ARM Workbench IDE is based around the Eclipse IDE, and provides additional features to support the ARM development tools that are provided in RVDS.
armar
The ARM librarian which enables you to create libraries of files, such as object files.
armasm
The ARM assembler. This converts ARM assembly language into machine code.
armcc
The ARM compiler for C and C++ code.
ArtiGrid
A power routing scheme, also referred to as Over The Cell.
Assertive Content and Backlight Control
Assertive Content and Backlight Control is a histogram-based power reduction engine, a constituent part of Assertive Display.
Assertive Display
Assertive Display is an advanced display management core incorporating backlight and content enhancement and power saving.
Assertive Display Control
Assertive Display Control describes the entire backlight pipeline of Assertive Display.
ATB
An AMBA bus protocol for trace data. The ATB is a common bus used by the trace components to pass trace data in a system in a data-agnostic format. A trace device can use an ATB to share CoreSight capture resources.
ATB bridge
A synchronous ATB bridge provides a register slice that meets timing requirements by adding a pipeline stage. It provides a unidirectional link between two synchronous ATB domains. An asynchronous ATB bridge provides a unidirectional link between two ATB domains with asynchronous clocks. This means it connects components in different clock domains.
atomicity
Describes actions that appear to happen as a single operation. In the ARM architecture, atomicity refers to either single-copy atomicity or multi-copy atomicity. The ARM Architecture Reference Manuals define these forms of atomicity.
ATPG
The process of using a specialized software tool to automatically generate manufacturing test vectors for an ASIC design.
authentication asynchronous bridge
Transfers authentication signals between two asynchronous clock domains.
authentication synchronous bridge
Transfers authentication signals between two synchronous clock domains.
Auto Brightness
Auto Brightness is an optional feature in Assertive Display which calculates optimal backlight brightness, ignoring internal backlight settings.
Auto Exposure
Auto Exposure is the automatic calculation of optimal sensor and lens settings prior to exposure, to control the brightness of an image.
Auto Focus
Auto Focus is the automatic calculation and control of lens focus distance, which aims to maximize the sharpness of the image subject.
Auto White Balance correction
Auto White Balance correction is the automatic equalization of color channels to correctly reproduce neutral tones, normally considered with respect to the color temperature in Kelvin.
Automatic Test Pattern Generation
The process of using a specialized software tool to automatically generate manufacturing test vectors for an ASIC design.
AWB
Auto White Balance correction is the automatic equalization of color channels to correctly reproduce neutral tones, normally considered with respect to the color temperature in Kelvin.
AWIDE
ARM Workbench IDE is based around the Eclipse IDE, and provides additional features to support the ARM development tools provided in RVDS.
AXI
An AMBA bus protocol that supports:
  • Separate phases for address or control and data.
  • Unaligned data transfers using byte strobes.
  • Burst-based transactions with only start address issued.
  • Issuing multiple outstanding addresses.
  • Out-of-order transaction completion.
  • Optional addition of register stages to meet timing or repropagation requirements.
The AXI protocol includes optional signaling extensions for low-power operation.
AXI Coherency Extensions
The AXI Coherency Extensions (ACE) provide additional channels and signaling to an AXI interface to support system level cache coherency.
AXI low-power interface
The low-power interface is an optional extension to the AXI protocol that targets two different classes of peripherals:
  • Any peripheral that has no power-down sequence, and that can indicate when its clocks can be turned off.
  • Any peripheral that requires a power-down sequence, and that can have its clocks turned off only after it enters a low-power state. The peripheral requires an indication from a system clock controller to indicate when to initiate the power-down sequence, and must then signal when it has entered its low-power state.
back-annotation
The process of applying timing characteristics from the implementation process onto a model.
Backlight
Backlight can refer to either the backlight of an LCD display, or more generally to the brightness of any emissive display.
banked register
A register that has multiple instances. A property of the state of the device determines which instance is in use. For example, the Security state might determine which instance is in use.
Base Platform Application Binary Interface
The Base Platform Application Binary Interface (BPABI) is the base standard for the interface between executable files, such as dynamic shared objects and DLLs, and the systems that execute them.
base porting layer
A platform-dependent base driver software component that communicates with the Mali GPU. For example, the base porting layer controls the Mali GPU registers. You implement, or port, the base porting layer onto different target platforms.
base register
A register specified by a load or store instruction that is used as the base value for the address calculation for the instruction. Depending on the instruction, an offset can be added to or subtracted from the base register value to form the address that is used for the memory access.
Base Standard Application Binary Interface
A collection of specifications, some open and some specific to the ARM architecture, that regulate the inter-operation of binary code in a range of execution environments for ARM cores. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
BCD file
In the context of RealView Debugger, a BCD file enables you to define the memory map and memory-mapped registers for a target development board or processor. ARM provides various BCD files with RVDS for ARM development boards.
beat
An alternative term for an individual transfer within a burst. For example, an INCR4 burst comprises four beats.
big-endian
In the context of the ARM architecture, big-endian is defined as the memory organization in which the least significant byte of a word is at a higher address than the most significant byte, for example:
  • A byte or halfword at a word-aligned address is the most significant byte or halfword in the word at that address.
  • A byte at a halfword-aligned address is the most significant byte in the halfword at that address.
BL
The black level is the value of a pixel when it is not illuminated. In this case, a CRT pixel would effectively be off because it must be illuminated. However, an LCD flat-screen pixel must be on, and black, to block the light from behind.
Black level
The black level is the value of a pixel when it is not illuminated. In this case, a CRT pixel would effectively be off because it must be illuminated. However, an LCD flat-screen pixel must be on, and black, to block the light from behind.
Board and Chip Definition file
In the context of RealView Debugger, a BCD file enables you to define the memory map and memory-mapped registers for a target development board or processor. ARM provides various BCD files with RVDS for ARM development boards.
board file
A debugger uses this term to refer to the top-level configuration file, normally called rvdebug.brd, that references one or more other configuration files. A board file contains:
  • The debug configuration (connection-level) settings.
  • References to the debug interface configuration file that identifies the targets on the development platform.
  • References to any Board and Chip Definition (BCD) files assigned to a debug configuration.
bounce
In an ARMv7 floating-point implementation that includes a VFP subarchitecture, a mechanism for handling floating point exceptions and instructions that are not supported by the hardware. A bounce generates an Undefined Instruction exception, and the exception handler can call support code to respond to the bounce.
boundary scan chain
A boundary scan chain is made up of serially connected devices that implement boundary scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain, connected between TDI and TDO, through which test data is shifted. A processor can contain several shift registers, enabling you to access selected parts of the device.
BPABI
The Base Platform Application Binary Interface (BPABI) is the base standard for the interface between executable files, such as dynamic shared objects and DLLs, and the systems that execute them.
branch folding
A technique where, on the prediction of a branch, the target instructions are completely removed from the instruction stream presented to the execution pipeline. Branch folding can significantly improve the performance of branches, and take the CPI for branches below one.
branch phantom
Branch target instructions that are speculatively executed, in parallel with the main instruction stream, as a result of branch folding.
branch prediction
The selection of a future execution path for instruction fetch. For example, after a branch instruction, the processor can choose to speculatively fetch either the instruction following the branch or the instruction at the branch target.
break-point
A debug event triggered by the execution of a particular instruction. It is specified by one or both of the address of the instruction and the state of the processor when the instruction is executed.
breakpoint
A debug event triggered by the execution of a particular instruction. It is specified by one or both of the address of the instruction and the state of the processor when the instruction is executed.
breakpoint unit
In the context of an ARM debugger, a unit in a chained breakpoint that combines with other breakpoint units to create a complex hardware breakpoint. In an M-profile processor, a hardware debug component that can be part of the Flash Patch and Breakpoint unit.
BSABI
A collection of specifications, some open and some specific to the ARM architecture, that regulate the inter-operation of binary code in a range of execution environments for ARM processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
burst
A group of transfers that form a single transaction. With AMBA protocols, only the first transfer of the burst includes address information, and the transfer type determines the addresses used for subsequent transfers.
byte lane strobe
A signal that determines which byte lanes are active, or valid, in a data transfer. Each bit of this signal corresponds to eight bits of the data bus.
byte swizzling
Re-arranging the order of bytes in a word or halfword.
byte-invariant
In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. The ARM architecture supports byte-invariant systems in ARMv6 and later versions.
CABC
Content Adaptive Backlight Control is a general term for power reduction methods such as the Assertive Content and Backlight Control (ACBC).
Cacheable
A data storage method in which, if a memory location to be written is not in cache memory, a cache line is allocated for the memory. The value of that memory is then loaded into the cache from main memory, and the new value for the location is written to cache.
CADI
The debug control and inspection API to a fast model.
Canonical Frame Address
In Debug With Arbitrary Record Format (DWARF), this is an address on the stack specifying where the call frame of an interrupted function is located.
captive thread
Captive threads are all threads that can be brought under the control of RVDS. Special threads, called non-captive threads, are essential to the operation of Running System Debug (RSD) and so are not under debugger control.
cast out
A cache line selected to be discarded to make room for a replacement cache line. This is required because of a cache miss. How it is selected for eviction is processor-specific.
CFA
In Debug With Arbitrary Record Format (DWARF), this is an address on the stack specifying where the call frame of an interrupted function is located.
chained breakpoint
In the context of an ARM debugger, a complex breakpoint that comprises multiple hardware breakpoint units.
chained tracepoint
In the context of an ARM debugger, a complex tracepoint that comprises multiple Tracepoint units.
channel interface
In an ECT device, the channel interface is one of the interfaces on CTI.
characterized
Designates a cell that includes timing data.
clean
A cache line that has not been modified while it is in the cache is said to be clean. To clean a cache is to write dirty cache entries to main memory.
clock gating
One way to reduce energy usage in the core is to remove power, which removes both dynamic and static currents, or to stop the clock of the core, which removes dynamic power consumption only and is referred to as clock gating.
Clocks Per Instruction
A measure of the number of computer instructions that can be performed in one clock cycle. It is also called Cycles Per Instruction. You can use this value to compare the performance of different processors that implement the same instruction set. The lower the value, the better the performance.
cluster
The preferred term for a group of cores. Typically, the set of cores in a cluster share some functionality, for example you might refer to a cluster that shares a single level 2 cache. To distinguish it from other clusters, you might describe this group of cores as a level 2 cluster.
CMM
In the context of an ARM debugger, a scripting language provided for compatibility with other debuggers. If you are writing new scripts, ARM recommends that you use the GNU Debugger (GDB) scripting commands because these offer more functionality in the ARM Debuggers.
CMSIS
CMSIS defines a common way to:
  • Access peripheral registers.
  • Define exception vectors.
  • The names of:
    • The registers of the core peripherals.
    • The registers of the core peripherals.
  • A device-independent interface for RTOS kernels, including a debug channel.
CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M Series processor. It also includes optional interfaces for middleware components comprising a TCP/IP stack and a flash file system.
coherence order
Data accesses from a set of observers to a byte in memory are coherent if accesses to that byte by the members of the set of observers are consistent with there being a single total order of all writes to that byte in memory by all members of the set of observers. This single total order of all writes to that byte is the coherence order for that byte.
coherent
Data accesses from a set of observers to a byte in memory are coherent if accesses to that byte by the members of the set of observers are consistent with there being a single total order of all writes to that byte in memory by all members of the set of observers. This single total order of all writes to that byte is the coherence order for that byte.
Cold reset
A Cold reset has the same effect as starting the processor by turning the power on. This clears main memory and many internal settings. Some program failures can lock up the core and require a Cold reset to restart the system.
Communications channel
The hardware used for communicating between the software running on the processor, and an external host, using the debug interface. When this communication is for debug purposes, it is called the Debug Communications Channel (DCC).
Condensed Reference Format
An ARM proprietary file format for specifying test vectors. Typically, ARM supplies a script to convert CRF format to Verilog Reference Format (VRF).
condition code check
The process of determining whether a conditional instruction executes normally or is treated as a NOP. For an instruction that includes a condition code field, that field is compared with the condition flags to determine whether the instruction is executed normally. For a T32 instruction in an IT block, the value of the ITSTATE register determines whether the instruction is executed normally.
condition code field
A four-bit field in an ARM instruction that specifies the condition under which the instruction executes.
condition flags
The condition flags are the N, Z, C, and V bits of PSTATE or of a Program Status Register (PSR).
conditional breakpoint
A breakpoint that has one or more condition qualifiers assigned. The breakpoint is activated when all assigned conditions are met, and either stops or continues execution depending on the action qualifiers that are assigned. The condition normally references the values of program variables that are in scope at the breakpoint location.
conditional execution
When a conditional instruction starts executing, if the condition code check returns TRUE, the instruction executes normally. Otherwise, it is treated as NOP.
CONSTRAINED UNPREDICTABLE
Where an instruction can result in UNPREDICTABLE behavior, the ARM architecture can specify a narrow range of permitted behaviors. This range is the range of CONSTRAINED UNPREDICTABLE behavior. All implementations that are compliant with the architecture must follow the CONSTRAINED UNPREDICTABLE behavior. However, software must not rely on any CONSTRAINED UNPREDICTABLE behavior.
Content Adaptive Backlight Control
Content Adaptive Backlight Control is a general term for power reduction methods such as the Assertive Content and Backlight Control (ACBC).
content synchronization operation
A context synchronization operation is one of:
In all versions of the ARM architecture:
  • The execution of an ISB instruction that does not fail its condition code check.
  • Taking an exception.
  • The return from an exception.
  • In addition, in ARMv8:
    • Exit from debug state.
    • Executing a DCPS instruction.
The architecture requires a context synchronization operation to guarantee visibility of any change to a System register.
context switch
The saving and restoring of computational state when switching between different threads or processes. Context switch describes any situation where the context is switched by an operating system and might or might not include changes to the address space.
context synchronization event
A context synchronization event is one of:
  • Performing an ISB operation. An ISB operation is performed when an ISB instruction is executed and does not fail its condition code check.
  • Taking an exception.
  • Returning from an exception.
  • Exit from debug state.
  • Executing a DCPS instruction.
  • Executing a DRPS instruction.

The architecture requires a context synchronization event to guarantee visibility of any change to a System register.

contrast ratio
The ratio between the absolute luminous levels of the brightest and darkest pixels that are simultaneously displayable on a display.
coprocessor
A processor, or conceptual processor, that supplements the main processor to carry out additional functions. In AArch32 Execution state, the ARM architecture defines an interface to up to 16 coprocessors, CP0-CP15.
In ARMv8, AArch32 state supports only conceptual coprocessors CP10, CP11, CP14, and CP15. In previous versions of the architecture, coprocessors CP0-CP7 are available for IMPLEMENTATION DEFINED features, and coprocessors CP8-CP15 are reserved for use by ARM.
In all architecture versions for the A and R architecture profiles, in AArch32 state:
  • CP15 instructions access the System registers. Some documentation describes this set of registers as the System Control Coprocessor.
  • CP14 instructions access System registers for debug, trace, and execution environment features,
  • The CP10 and CP11 instruction space is for Advanced SIMD and floating-point instructions if supported, including the instructions for accessing the Advanced SIMD and floating-point System registers.
core
Core is used to describe a single processing unit. In the applications processor area we can further define core as something that has exclusive use of its own program counter (PC). ARM Architecture Reference Manuals describe this entity as a PE.
core module
In the context of an ARM integrator development board, an add-on development board that contains an ARM processor and local memory. Core modules can run standalone, or can be stacked onto integrator development boards.
core register
Processing registers used in AArch32 Execution state, comprising:
  • 13 general-purpose registers, R0 to R12, that software uses for all data processing when using the base instruction set instructions.
  • SP, the stack pointer, that can also be referred to as R13.
  • LR, the Link Register, that can also be referred to as R14.
  • PC, the Program Counter, that can also be referred to as R15.
In some situations, software can use SP, LR, and PC for processing. The instruction descriptions include any constraints on the use of SP, LR, and PC.
core reset
Also known as a Warm reset. Initializes most of the processor functionality, excluding the debug controller and debug logic. This type of reset is useful if you are using the debugging features of a processor.
CoreSight
ARM on-chip debug and trace components, that provide the infrastructure for monitoring, tracing, and debugging a complete System on Chip.
CoreSight ECT
A modular system that supports the interaction and synchronization of multiple triggering events with an SoC. It comprises:
  • Cross Trigger Interface (CTI).
  • Cross Trigger Matrix (CTM).
CoreSight ETB
A Logic block that extends the information capture functionality of a trace macrocell.
CoreSight ETM
A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.
CoreSight STM
A trace source that is designed primarily for high-bandwidth trace of instrumentation embedded into software. This instrumentation is made up of memory-mapped writes to the STM, which carry information about the behavior of the software.
CoreSight TMC
Controls the capturing or buffering trace that is generated by trace sources within a system. The TMC receives trace from an ATB interface and can be configured to perform one of the following:
  • Route the trace out over an AXI master interface, to allow trace to be captured in system memory or in other peripherals.
  • Capture the trace in a circular buffer in dedicated SRAM.
  • Buffer the trace in a First In First Out (FIFO) style, to smooth over peaks in trace bandwidth.
Cortex Microcontroller Software Interface Standard
The Cortex Microcontroller Software Interface Standard (CMSIS) defines: a common way to:
  • Access peripheral registers.
  • Define exception vectors.
  • The names of:
    • The registers of the core peripherals.
    • The core exception vectors.
  • A device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M Series processor. It also includes optional interfaces for middleware components comprising a TCP/IP stack and a flash file system.
CPI
A measure of the number of computer instructions that can be performed in one clock cycle. It can be referred to as Clocks Per Instruction or Cycles Per Instruction. You can use this value to compare the performance of different processors that implement the same instruction set. The lower the value, the better the performance.
CPSR
In AArch32 state, the register that holds the current program status.
CRF
An ARM proprietary file format for specifying test vectors. Typically, ARM supplies a script to convert CRF format to Verilog Reference Format (VRF).
cross-path blocking
This occurs when a divergent node has congestion on one of its output nodes which blocks bus traffic to its other output nodes..
Cross Trigger Interface
Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.
Cross Trigger Matrix
Part of an Embedded Cross Trigger (ECT) device. In an ECT device, the CTM combines the trigger requests generated by CTIs and broadcasts them to all CTIs as channel triggers.
CTI
Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.
CTM
Part of an Embedded Cross Trigger (ECT) device. In an ECT device, the CTM combines the trigger requests generated by CTIs and broadcasts them to all CTIs as channel triggers.
Current Program Status Register
In AArch32 state, the register that holds the current program status.
Cycles Per Instruction
A measure of the number of computer instructions that can be performed in one clock cycle. It is also called Clocks Per Instruction. You can use this value to compare the performance of different processors that implement the same instruction set. The lower the value, the better the performance.
DA
In RealView Debugger, the debug agent provides target-side support for Running System Debug (RSD). The debug agent can be a thread or be built into the RTOS. The debug agent and RealView Debugger communicate with each other using the DCC. This passes data between the debugger and the target using a hardware debug interface, without stopping the program or entering debug state.
DAP
In an external debugger, a block that acts as a master on a system bus and provides access to the debug target.
DAPBUS interconnect
The DAPBUS interconnect connects a Debug Port (DP) to the Access Ports (APs) in a CoreSight DAP.
Data Abort
An indication to the core of an attempted data access that is not permitted. The Data Abort might be generated by access permission checks performed by the memory system on the core, or might be signaled by the memory system.
data breakpoint
In the context of the ARM debugger, a hardware breakpoint that activates when an access to a specified location meets a set of specified conditions. The conditions can include a check for a specific data value being accessed at the given location.
Data Timing Module
In the context of physical IP, a data timing module that synchronizes incoming and outgoing data. The DTM is a component of PHY to include I/Os and PLL.
data-active write transaction
A transaction that has completed the address transfer or leading write data transfer, but has not completed all its data transfers.
Daughterboard Configuration Controller
A microcontroller on a Versatile Express LogicTile or CoreTile daughterboard. It controls the power up and configuration of the daughterboard in conjunction with the Motherboard Configuration Controller (MCC) on the Motherboard Express motherboard.
DBGTAP
A debug control and data interface based on IEEE 1149.1 JTAG Test Access Port (TAP). The interface has four or five signals.
DCC
A channel that carries data between a debugger and debug logic in the target processor. It can do this without stopping the program flow or causing entry to Debug state, but can also be used when the target is in Debug state. The DCC is part of the debug register interface of the target.
DCU
The display calibration unit is responsible for calibrating colors and brightness tones in a display.
Debug Access Port
In an external debugger, a block that acts as a master on a system bus and provides access to the debug target.
debug agent
In the RealView Debugger, the debug agent provides target-side support for Running System Debug (RSD). The debug agent can be a thread or be built into the RTOS. The debug agent and RealView Debugger communicate with each other using the DCC. This passes data between the debugger and the target using a hardware debug interface, without stopping the program or entering debug state.
Debug Communications Channel
A channel that carries data between a debugger and debug logic in the target processor. It can do this without stopping the program flow or causing entry to Debug state, but can also be used when the target is in Debug state. The DCC is part of the debug register interface of the target.
debug configuration
In the context of an ARM debugger, a debug configuration defines a debugging environment for the development platform that is accessed through a particular debug interface. Multiple debug configurations can be created for a debug interface, each providing a separate debugging environment to different development platforms, or different debugging environments to the same development platform.All debug configurations are stored in the main debugger board file. Each configuration might reference one or more BCD files.
debug event
A debug event is some part of the process being debugged that causes the system to notify the debugger. Debug events can be synchronous or asynchronous. Breakpoints, the BKPT instruction, and Watchpoints are all synchronous debug events.
debug illusion
The view of the software being debugged that a debugger presents to its user. The features of the debug illusion include:
  • Mapping between assembler code and source code, including displaying assembler and source code simultaneously if necessary.
  • Support for source-level stepping and breakpoints.
  • Visibility of the source-level function call stack, even when called functions are generated inline.
  • Display of variable values and structure field values, even when these values migrate between various locations. This includes displaying registers and the stack.
debug interface
In the context of RealView Debugger, the debug interface identifies the targets on your development platform, and provides the mechanism that enables RealView Debugger to communicate with those targets. The debug interface corresponds directly to a piece of hardware or a software simulator.
Debug Test Access Port
A debug control and data interface based on IEEE 1149.1 JTAG Test Access Port (TAP). The interface has four or five signals.
Default NaN mode
In floating-point operation, a mode in which all operations that result in a NaN return the default NaN, regardless of the cause of the NaN result. This mode is compliant with the IEEE 754 standard but implies that all information contained in any input NaNs to an operation is lost.
defective pixel
A faulty pixel which does not perform correctly, either a hot (white) pixel or dead (black) pixel.
denormalized value
The IEEE 754-2008 standard term for a floating-point operand with a zero exponent and a nonzero fraction field. ARM documentation describes these operands as denormal or denormalized, as defined by the IEEE 754-1985 standard.
Design Simulation Model
A functional simulation model of the device that is derived from the Register Transfer Level (RTL) but that does not reveal its internal structure. The DSM does not model any features added during synthesis such as internal scan chains.
development platform
Contains the components, either hardware or simulated, that you use to develop your application. It can include:
  • A development board, such as an Integrator or CP.
  • Peripherals.
  • One or more processors that implement the ARM architecture.
  • CoreSight components.
Development Studio 5
The suite of software development tools, together with supporting documentation and examples, that enable you to write and debug applications for the ARM family of processors. DS-5 supersedes RealView Development Suite.
device
In the context of an ARM debugger, a component on a target. The device contains the application that you want to debug.
Device tree
A device tree is a data structure that describes the hardware configuration. It includes information about processors, memory buses and banks, interrupt configuration, and peripherals. The data structure is organized as a tree with a single root node named /. Except for the root node, each node has a single parent. Each node has a name and can have any number of child nodes. Nodes can also contain named properties values with arbitrary data, and they are expressed in key-value pairs. The device tree data format follows the conventions defined in IEEE standard 1275.
Device Validation Suite
A set of tests to check the functionality of a device against that defined in the Technical Reference Manual.
Digital Gain
Digital gain describes the multiplication of pixel value after analog-to-digital conversion.
Digital Image Stabilization
The process by which image blur that is caused by camera movement is removed using digital filters.
Direct-mapped cache
A one-way set-associative cache. Each cache set consists of a single cache line, so cache look-up selects and checks a single cache line.
Direct read
A direct read of a System register is a read performed by a System register access instruction.
Direct write
A direct write of a System register is a write performed by a System register access instruction.
Dirty
A line in a Write-Back cache that has been modified while it is in the cache. Typically, a cache line is marked as dirty by setting the dirty bit to 1.
DIS
Digital image stabilization is the process by which image blur that is caused by camera movement is removed using digital filters.
Display Calibration Unit
The display calibration unit is responsible for calibrating colors and brightness tones in a display.
DNM
A value that must not be altered by software. These fields read as UNKNOWN values, and must only be written with the value read from the same field on the same processor.
Do-Not-Modify
A value that must not be altered by software. These fields read as UNKNOWN values, and must only be written with the value read from the same field on the same processor.
doubleword
A 64-bit data item. Doublewords are normally at least word-aligned in ARM systems.
doubleword-aligned
A data item having a memory address that is divisible by eight.
DP
A faulty pixel which does not perform correctly, either a hot (white) pixel or dead (black) pixel.
draw mode
In the context of graphics processing, one of the different ways to specify the primitives to draw. These different ways are called draw modes. The primitives can be specified individually or as a connected strip or fan. They can also be either:non-indexed, meaning that vertices are passed in a vertex array and processed in order. indexed, meaning that vertices are passed as indices into a vertex array.
DRC
Dynamic range compression describes any method which reduces the digital range that is required to represent captured tones in an image.
DS-5
The suite of software development tools, together with supporting documentation and examples, that enable you to write and debug applications for the ARM family of processors. DS-5 supersedes RealView Development Suite.
DS-5 Debugger
An ARM software development tool that enables you to make use of a debug agent to examine and control the execution of software running on a debug target. It is fully integrated into Eclipse for DS-5.
DSM
A functional simulation model of the device that is derived from the Register Transfer Level (RTL) but that does not reveal its internal structure. The DSM does not model any features added during synthesis such as internal scan chains.
DTM
In the context of physical IP, a data timing module that synchronizes incoming and outgoing data. The DTM is a component of PHY to include I/Os and PLL.
DVS
A set of tests to check the functionality of a device against that defined in the Technical Reference Manual.
Dynamic Range
The ratio between the brightest and darkest tones that can be represented by a sensor. The ratio is limited by saturation and noise.
Dynamic Range Compression
Dynamic range compression describes any method which reduces the digital range that is required to represent captured tones in an image.
Early-Z
The Early-Z system checks that the depth of the pixel being processed is not already occupied by a nearer pixel. If it is occupied, it does not execute the fragment shader. Z testing typically happens after the fragment shader, however usually this shader is the most computationally expensive so should be avoided if the fragment is not visible in the scene.
Eclipse for DS-5
Eclipse for DS-5 is based around the Eclipse IDE, and provides additional features to support the ARM development tools that are provided in DS-5.
ECT
A modular system that supports the interaction and synchronization of multiple triggering events with an SoC. It comprises:
  • Cross Trigger Interface (CTI).
  • Cross Trigger Matrix (CTM).
EGL
A standardized set of functions that communicate between graphics software, such as OpenGL ES or OpenVG drivers, and the platform-specific windowing system that displays the image.
ELR
In AArch64 state, there is a dedicated LR for each implemented Exception level, called the Exception Link Register (ELR) for that Exception level, for example, ELR_EL1. The Exception Link Register holds the exception return address.
embedded assembler
Embedded assembler is assembler code that is included in a C or C++ file, and is separate from other C or C++ functions.
Embedded Cross Trigger
A modular system that supports the interaction and synchronization of multiple triggering events with an SoC. It comprises:
  • Cross Trigger Interface (CTI).
  • Cross Trigger Matrix (CTM).
Embedded Trace Buffer
A Logic block that extends the information capture functionality of a trace macrocell.
Embedded Trace Macrocell
A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.
Embedded-System Graphics Library
A standardized set of functions that communicate between graphics software, such as OpenGL ES or OpenVG drivers, and the platform-specific windowing system that displays the image.
EmbeddedICE logic
An on-chip logic block that provides TAP-based debug support for an ARM processor. It is accessed through the DAP on the ARM processor.
EmbeddedICE-RT
Hardware provided by an ARM processor to aid debugging in real time.
emulator
In the context of target connection hardware, an emulator provides an interface to the pins of a real processor. It emulates the pins to the external world, and enables you to control or manipulate signals on those pins.
endianness
The scheme that determines the order of the successive bytes of data in a larger data structure when that structure is stored in memory.
ESSL
A programming language that isused to create custom shader programs that can be used in a programmable pipeline, on the Mali GPU. You can also use pre-defined library shaders, which are written in ESSL.
ESSL compiler
The compiler that translates shaders written in ESSL, into binary code for the shader units in the Mali GPU. There are two versions of the ESSL compiler:
  • The on-target compiler.
  • The Offline Compiler.
ETB
A Logic block that extends the information capture functionality of a trace macrocell.
ETM
A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.
ETV
Extended Target Visibility enables RealView Debugger to access features of the underlying target such as chip-level information provided by the hardware manufacturer or SoC designer.
Event
In the context of an ARM trace macrocell, events can be:
  • Simple -An observable condition that a trace macrocell can use to control aspects of a trace.
  • Complex -A Boolean combination of simple events that a trace macrocell can use to control aspects of a trace.
event asynchronous bridge
A fixed component that synchronizes events on a single channel from the slave domain to the master domain. In addition, the event acknowledge from the master domain is synchronized and signaled to the slave domain.
exception
A mechanism to handle a fault, error event, or external notification. For example, exceptions handle external interrupts and UNDEFINED instructions.
Exception level
In the ARMv8 architecture, a program executes at one of four Exception levels. In AArch64, the Exception level determines the level of execution privilege. Exception levels provide a logical separation of software execution privilege that applies across all operating states of the ARMv8 architecture. System software determines the Exception level, and therefore the level of privilege, at which software runs.
Exception Link Register
In AArch64 state, there is a dedicated LR for each implemented Exception level, called the Exception Link Register (ELR) for that Exception level, for example, ELR_EL1. The Exception Link Register holds the exception return address.
exception vector
A fixed address that contains the address of the first instruction of the corresponding exception handler.
exceptional state
In an ARMv7 implementation that includes a VFP subarchitecture, in floating-point operation, if the floating-point hardware detects an exceptional condition, the ARM floating-point implementation sets the FPEXC bit and loads a copy of the exceptional instruction to the FPINST register. When in the exceptional state, the issue of a trigger instruction to the floating-point extension causes a bounce.
execution vehicle
A part of the debug target interface that processes requests from the client tools to the target.
execution view
The address of regions and sections after the image is loaded into memory and started execution.
explicit access
A read from memory, or a write to memory, generated by a load or store instruction executed by the core. Reads and writes generated by hardware translation table accesses are not explicit accesses.
Extended Target Visibility
Extended Target Visibility enables RealView Debugger to access features of the underlying target such as, for example, chip-level information provided by the hardware manufacturer or SoC designer.
eXtensible Verification Component
A model that provides system or device stimulus and monitor responses.
external abort
An abort generated by the external memory system.
Was this page helpful? Yes No