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Why does the Configuration and Control Register (CCR) not have the NONBASETHRDENA bit in Armv8-M?

Article ID: 131328911

Published date: 07 Nov 2017

Last updated: -

Applies to: ARMv8-M

Problem/Question

Why does the Configuration and Control Register (CCR) not have the NONBASETHRDENA bit in Armv8-M?

Scenario

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Answer

In Armv7-M the usual behavior is that an exception return to Thread mode is allowed only if no other exceptions are active. Enabling the NONBASETHRDENA feature in the CCR register disables this check.

Armv8-M changes the control scheme so that a return to Thread mode is always permissible, even if there are other active exceptions.

To provide backward compatibility to software, CCR bit[0] is RES1 in Armv8-M. Any legacy software that relies on this feature sees the illusion of it always being enabled.

Workaround

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Example

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Related Information

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