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How are Secure and Non-secure NVICs Accessed in Armv8-M Processors?

Article ID: 165521430

Published date: 13 Feb 2018

Last updated: -

Applies to: ARMv8-M

Problem/Question

How are Secure and Non-secure NVICs accessed in Armv8-M processors?

Scenario

N/A

Answer

When the Security Extension is implemented, Armv8-M processors have two Nested Vectored Interrupt Controllers (NVICs):

  • A Secure NVIC for Secure state.

  • A Non-secure NVIC for Non-secure state.

In Secure state or Non-secure state, the memory maps are backward-compatible with the Armv7-M architecture. This means that the NVIC registers are banked. In other words, the following registers share the same base address of the NVIC register page:

  • The Non-secure NVIC for Non-secure state.

  • The Secure NVIC for Secure state.

Consequently, the core header files for Armv8-M processors use the same base address and the same set of Application Program Interfaces (APIs) for Secure NVICs and Non-secure NVICs. For example:

/*! NVIC Base Address */

#define NVIC_BASE (SCS_BASE + 0x0100UL)

...

/*! NVIC configuration structure */

#define NVIC ((NVIC_Type*) NVIC_BASE)

...

/*! The same set of APIs for NVIC access */

__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn);

__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn);

__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn);

__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn);

__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn);

__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn);

__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);

__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn);

In addition to the Security Extension, two extensions are added to the Armv8-M architecture:

  • In Secure state, it is possible to access the Non-secure NVIC, which has an alias in the memory map. For example:

/*! Non-secure NVIC Alias Base Address in Secure Mode only */

#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)

/*! Non-secure NVIC Configuration Structure Alias in Secure Mode only */

#define NVIC_NS ((NVIC_Type *)NVIC_BASE_NS)

This Non-secure NVIC alias can be accessed by using a dedicated set of APIs, which have the pattern of TZ_NVIC_* as below:

__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn);

__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn);

__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn);

__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn);

__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn);

__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn);

__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority);

__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn);

Note: This alias is invisible for Non-secure state and works as RAZ/WI.

  • The NVIC_ITNSn registers defined in the NVIC_Type are only accessible in Secure state. They are RAZ/WI when accessed in Non-secure state. They are treated as place holders in the header file when viewed from Non-secure state.

/**

\Brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).

*/

typedef struct

{

...

/*!< Offset: 0x280 (R/W) Interrupt Non-secure State Register */

__IOM uint32_t ITNS[16U];

...

} NVIC_Type;

The following APIs are only available in Secure state for NVIC_ITNSn registers:

__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn);

__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn);

__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn);

Workaround

N/A

Example

N/A

Related Information

  • Armv8-M Architecture Reference Manual

None.

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