Trusted Base System Architecture-Client
The Trusted Base System Architecture (TBSA) specifies hardware requirements for implementing a client SoC as a trusted platform, compliant with key industry standards and specifications.
Trusted Base System Architecture
Trusted Base Boot Requirements-Client
Trusted Board Boot Requirements (TBBR) defines a trusted boot process for client SoCs, compliant with key industry standards and specifications.
The Trusted Firmware on Arm Open Source Project provides support for trusted boot. You may also be interested in the Isolation using virtualization in the Secure world white paper.
TrustZone Media Protection
TrustZone Media Protection (TZMP) is a system architecture for implementing protected media paths. System and software architecture specifications are available.
Power State Coordination Interface
The Power State Coordination Interface (PSCI) defines a standard interface for power management that can be used by OS vendors for supervisory software, working at different levels of privilege on an Arm device.
The aim of this standard is to ease the integration between supervisory software from different vendors working at different privilege levels.
Arm Power State Coordination Interface
System Control and Management Interface
This document describes the System Control and Management Interface (SCMI), which is a set of operating system-independent software interfaces that are used in system management.
SCMI is extensible and currently provides interfaces for:
- Discovery of supported interfaces.
- Power domain management.
- Performance management.
- Clock management.
- Sensor management.
Arm System Control and Management Interface
System Architecture for Power Management
Power Control System Architecture
Describes an approach to the Power Control System Architecture (PCSA) of SoCs, based on Arm components.
There are two intended audiences for this specification:
- SoC architects and designers designing power managed System-on-Chip (SoC), based on Arm components.
- Component designers incorporating Arm low-power interfaces for clock and power control, with the aim of compatibility to the system integration principles outlined in this specification.