System Architecture Overview

In addition to development of processor architecture, standardization across areas of system architecture is a key aspect of a rich re-usable ecosystem. Three of these areas are closely related to processor and operating system development:
  • System timer support is included in recent A-profile, R-profile and M-profile architectures.
  • Standardization of interrupt controller support.
  • IOMMU support for virtualization.
System instructions in the ARMv8-A and ARMv8-R architectures provide predictable low latency access in the programmers’ model for critical timer and interrupt handling functions.

Timer support is specified as part of the A-profile, R-profile and M-profile architectures.

ARM Generic Interrupt Controller

The ARM Generic Interrupt Controller (GIC) architecture has two forms in general use with the A-profile that are also applicable to the R-profile:

  • GICv2 is a memory mapped solution supporting up to eight processors.
  • GICv3 offers support for much higher interrupt counts and larger numbers of processors. This version includes support for the System registers in ARMv8-A and ARMv8-R designs. 
  • GICv4 adds supports the direct injection of virtual interrupts.
The M-profile has its own NVIC interrupt controller as an integral part of the M-profile architecture.

IOMMU Support

IOMMU support allows systems to share A-profile page tables with peripherals, providing virtual device support compatibility at the system level with the ARM architecture memory model. Similar to GIC developments, support is evolving to cater for the increasing complexity in larger systems:

  • SMMUv2 is a register-based architecture in general use today.
  • SMMUv3 is under development with key partners across the ecosystem. This version scales to much larger systems and includes support for features such as the ATS and PRI functionality defined in the PCIe standard. The specification is expected to be published in 2016.