AMBA CHI	The AMBA CHI (Coherent Hub Interface) specification defines the interfaces for the connection of fully coherent processors. It is appropriate for a wide range of applications that require coherency, including mobile, networking, automotive, and data centers. The AMBA CHI specification separates the protocol and transport layers to allow differing implementations to provide the optimal trade-off between performance, power and area.
AMBA CHI C2C	AMBA CHI C2C is an extension to CHI. It defines how the on-chip CHI protocol is packetized for transport over a chip(let)-to-chip(let) link. It targets advanced heterogeneous systems and Arm-based coherent SMP, providing a single and unified interface for device attach for maximum interoperability.
AMBA AXI	The AMBA AXI (Advanced eXtensible Interface) specification defines the protocols to implement high frequency, high bandwidth interconnect designs across a wide range of applications, including mobile, consumer, networking, automotive, and embedded.
AMBA ACE	The AMBA ACE (AXI Coherency Extension) is an extension to AXI for system-wide coherency across multicore clusters. Note that ACE is superseded by CHI and is no longer recommended for new designs.
AMBA AHB	The AMBA AHB (Advanced High-performance Bus) specification defines an interface protocol most widely used with Cortex-M processors, for embedded designs and other low latency SoCs.
AMBA APB	AMBA APB is highly compact, low power and allows configuration and low bandwidth traffic to be isolated from high performance interconnects. APB supports low bandwidth transactions required to access configuration registers and low bandwidth data traffic in peripherals.
AMBA AXI-Stream	AMBA AXI-Stream defines an interface for unidirectional data transfers with greatly reduced signal routing, making it ideal for implementation in FPGA.
AMBA CXS	The AMBA CXS specification defines a credited, non-blocking streaming interface protocol, used in point-to-point packetized communications. It is optimized for the transport of CCIX and CXL packets between an on-chip interconnect and a PCIe controller. CXS is also optimized for wide interfaces, which enables passing packets to a high data rate external interface and merging of multiple packets into a single transfer.
AMBA DTI	The AMBA DTI (Distributed Translation Interface) protocol specification aligns with the Arm System MMU architecture, to define a scalable, distributed messaging protocol for translation services. DTI is a point-to-point protocol and defines the communication between a TBU or PCIe Root Port implementing ATS, and a TCU.
AMBA LTI	The AMBA LTI (Local Translation Interface) protocol specification aligns with the Arm System MMU architecture and complements AMBA DTI to provide higher performance and more efficient translation services. LTI is a point-to-point protocol and defines the communication between an I/O device and a TBU.
AMBA ATB	The AMBA ATB specification defines a data-agnostic interface for transferring trace information between components in a trace system. The trace components and bus sit in parallel with the peripherals and interconnect and provide visibility for debug purposes.
AMBA LPI	The AMBA LPI (Low Power Interface) specification defines the Q-Channel and P-Channel interfaces, designed to manage clock and power features of SoC components.
AMBA ATP	The AMBA Adaptive Traffic Profiles (AMBA ATP) is a synthetic traffic framework and is capable of modeling systems' high-level memory access behaviour in a concise, simple and portable way. Traffic Profiles can be used across multiple tools and design/verification environments to assist with the design and verification of complex SoCs.
AMBA GFB	The AMBA Generic Flash Bus (AMBA GFB) specification outlines a method of developing memory controllers for Non-Volatile Memory, which allows easy migration between different foundry processes, saving development resources.

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