SMMU (otherwise known as IOMMU) support allows systems to share A-profile page tables with peripherals, providing virtual device support compatibility at the system level with the Arm architecture memory model. Similar to GIC developments, support is evolving to cater for the increasing complexity in larger systems:
- SMMUv2 is a register-based architecture, suited to smaller-scale systems.
- SMMUv3 extends the architectural concepts of earlier SMMU architectures by adding configuration stored in memory, which enables support of significantly larger IO systems. SMMUv3 also provides enhanced support for PCI Express-based systems, including PCIe ATS and PRI features.