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Arm DSU-120AE enables DynamIQ technology for Armv9.2 Automovie Enhanced (AE) CPUs, with expanded support for up to 14 cores in a single cluster (with no additional restriction on the number of big or little cores) and up to 32MB L3. Alongside performance scalability, it also introduces new power management features.
The DynamIQ Shared Unit 120 (DSU-120) is the backbone of the Cortex Compute Cluster. Combining various Cortex cores in a big.LITTLE configuration.
Arm Cortex-A720AE is the highest performance Cortex-A processor for safety-critical tasks. Cortex-A720AE meets the most complex and demanding compute and functional safety needs in next-generation AI-accelerated software-defined vehicles.
First generation Armv9.2 premium efficiency, out-of-order CPU. It can be combined with Cortex-A520 and Cortex-X4 in a big.LITTLE configuration.
Cortex-A725 is a second generation Armv9.2 premium efficiency, out-of-order CPU. It can be combined with Cortex-X925 and Cortex-A520 in a big.LITTLE configuration with DSU-120.
The Cortex-A520 CPU is the first Armv9.2-A "LITTLE" processor, offering high energy efficiency in a small area footprint and it can be combined with Cortex-A CPUs in a big.LITTLE configuration.
Cortex-A715 is the second-generation Armv9 “big” Cortex CPU designed for industry-leading efficient performance.
The Cortex-A76AE processor brings high levels of safety with Dual Core Lock-Step (DCLS) capabilities.
The Arm Cortex-A76 CPU is the second-generation premium core built on DynamIQ technology.
The Arm Cortex-A78 CPU is the fourth-generation premium core built on DynamIQ technology
The Arm Cortex-A77 CPU is the third-generation premium core built on DynamIQ technology.
The Cortex-A73 is a highly efficient premium processor from Arm.
The Cortex-A78C CPU provides a scalable solution with advanced security features and large big-core configurations.
The Cortex-A75 processor is the first Armv8.2-A high-performance application CPU.
The Cortex-A710 CPU is the first generation Armv9 "big" processor. Offering a balance of performance and efficiency to multiple devices.
The MPS4 board is an FPGA prototyping platform, supporting FPGA implementations of Arm Corstone subsystems, including Cortex-A, Cortex-R, and Cortex-M processors.
The Cortex-A65 is a multithreaded Cortex-A CPU.
A 64-bit multi-threaded CPU with Split-Lock capability for mixed-criticality applications.
The Cortex-A510 CPU is the first generation Armv9 high efficiency "LITTLE" processor.
Provides configurable CoreSight SoC components for the generation of debug, trace, cross-trigger and time-stamping functionality.
The Arm Mali-G52 is the second Bifrost-based mainstream GPU from Arm.
The Arm Mali-G310 is the first generation Valhall based ultra efficient GPU.
The Arm Mali-G57 GPU is the first generation Valhall-based GPU for the mainstream market.
The Arm Mali-G51 High Area Efficiency GPU is the first GPU to take the Bifrost graphics architecture to mainstream devices.
The Arm Mali-G510 is the second generation Valhall based GPU for mainstream market devices.
The Arm Mali-G68 GPU based on the Mali Valhall architecture, brings the features of a premium GPUs to the sub premium market.
The Arm Mali-G710 GPU is the third generation Valhall based premium GPU for superior gaming experiences.
Mali-G715 delivers a range of new graphics features for high performance and energy efficiency across premium mobile devices.
Mali-G71 is the first premium level GPU to implement the Bifrost architecture.
Premium Arm GPU based on the Arm’s 5th-generation architecture to deliver improved performance and energy efficiency on all form factors.
Mali-G625 is a premium Arm GPU built on the 5th Gen Arm GPU Architecture to deliver improved performance and energy efficiency on all form factors.
Arm Mali-G72 is the second generation Bifrost-based GPU for high performance products.
Premium Arm GPU based on the Arm 5th-generation architecture, delivering improved performance and energy efficiency on all form factors.
The Arm Mali-G78 GPU is the second generation high performance GPU based on the Mali Valhall architecture.
PL080 is a synthesizable DMA controller supporting one AHB manager interface and eight DMA channels.
PL011 is a synthesizable Universal Asynchronous Receiver Transmitter (UART) serial port controller.
The Arm Mali-G76 GPU is the third generation high performance GPU based on the Mali Bifrost architecture.
TrustZone for Cortex-M enables robust levels of software security protection in a range of low power, low cost IoT devices.
PL111 is a synthesizable color LCD controller supporting an AHB manager and subordinate interface and driving TFT and STN, single and dual panel displays.
The Arm Neoverse CMN-700 Coherent Mesh Network is a high bandwidth, low-latency system interconnect that supports a range of applications.
Accelerating the transformation to a scalable cloud-to-edge infrastructure.
The Arm SecurCore SC300 processor is designed for high-performance smartcard and embedded security applications.
PL320 is an Inter-processor communications module for servicing interrupts. It pre-dates the GIC architecture.
PL192 is an advanced vectored interrupt controller supporting up to 32 vectored interrupts with programmable priority level and masking.
The AHB MC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral. The AHB MC takes advantage of the newly developed Dynamic Memory Controller (DMC) and Static Memory Controller (SMC). The AHB MC has four AHB ports with access to the external memory. Each AHB port has a bridge interface to the memory controllers. There is a separate AHB port to configure the memory controllers. Specific configurations of the SMC and DMC are instantiated to target specific memory devices.
Leading performance efficiency for Cloud-to-Edge infrastructure
The Arm SecurCore SC000 processor is designed for the highest-volume smartcard and embedded security applications.
The PL241 AHB MC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral. The AHB MC takes advantage of the newly developed Dynamic Memory Controller (DMC) and Static Memory Controller (SMC). The AHB MC has four AHB ports with access to the external memory. Each AHB port has a bridge interface to the memory controllers. There is a separate AHB port to configure the memory controllers. Specific configurations of the SMC and DMC are instantiated to target specific memory devices.