Cortex-A7 POP is the most widely licensed POP IP and is available on 40nm and 28nm process technologies on multiple foundries. The Cortex-A7 POP is available in high performance and low power versions. The high performance version can achieve over 2.0GHz in 28nm technology.
The low-power version can achieve over 1.0GHz performance while taking up less than 2 mm2 of area . The POP IP package consists of Cortex-A optimized logic IP and high performance fast cache instances (FCI) along with a comprehensive RTL-GDS flow supporting major EDA vendors.
Cortex-A53 POP is a highly successful implementation solution for ARM Cortex-A53 CPU. Products based on Cortex-A53 processor are shipping in high volumes in the smart-phone/tablet , DTV and consumer electronics segments . Cortex-A53 POP is available on 28nm and 16nm FinFET process technologies. POP technology enable customers to implement Cortex-A53 processors in multiple configurations- from a low power LITTLE CPU in a big.LITTLE system to a high-performance/low-power combination in ‘octacore’ systems to a stand-alone high-performance quad-core CPU.
The Artisan POP IP supports multiple L1/L2 cache sizes as well as support for ECC . The fast cache instances in Cortex-A53 support a special ‘Light Sleep Mode’ in conjunction with the Cortex-A53 CPU . The POP IP package consists of Cortex-A optimized logic IP as well as high performance fast cache instances (FCI), along with a comprehensive RTL-GDS flow supporting major EDA vendors.
Cortex-A72 POP IP is a high performance implementation for Cortex-A72 on 16nm FinFET technology. Targeted at mobile and infrastructure markets, it can help customers achieve up to 3.0GHz performance in silicon while consuming very low power in a small area. Artisan POP IP for Cortex-A72 supports ECC as well as multiple L1/L2 configurations.
Developed in conjunction with Cortex-A72 CPU architects , Cortex-A72 POP includes specially customized memories which tie the physical IP and RTL closely to deliver a highly optimized integrated solution. The POP IP package consists of Cortex-A optimized logic IP, high performance fast cache instances(FCI), and specially customized memories along with a comprehensive RTL-GDS flow supporting major EDA vendors.