Cortex-A Series Characteristics
All Armv7-A and Armv8-A based processor cores featured in the current Arm processor portfolio supports Arm's multicore technologies.
- Up to eight-core implementations for all DynamIQ based processors
- Up to quad-core implementation for all processors using Armv7-A and the original Armv8-A specification
Key features of the Cortex-A family of devices:
- Scalable clusters supporting single and multi-core configurations
- RISC cores with support for Armv7-A and Armv8-A architecture
- Full backward compatibility with code from previous Arm processors
- VFP and NEON units to execute floating-point and Advanced SIMD instruction sets
- Optional Cryptographic accelerator engines supporting algorithms like AES, SHA1 and SHA2-256
- Memory Management Support (MMU) supporting virtual address and physical address spaces with various page sizes
- Hardware translation table walking for virtual to physical address translation
- Big-endian and little-endian data access support
- Unaligned access support for basic load/store instructions
Cortex-A Series Programmer's Guide for Armv7-A
Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.Get the guide
Cortex-A Series Programmer's Guide for Armv8-A
Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.Get the guide
Porting to Arm 64-bit
If you are migrating from an Armv7 architecture based design to the Armv8 64-bit A64 instruction set, we provide a porting guide to help you.Get the guide
Development Tools for Cortex-A
Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.Development Tools
Cortex-A Safety Documents Package
For customers who needs to safety certify their end products, Arm provides a Safety Documentation Package for silicon developers and safety certified toolchain to accelerate the time to market.
Armv8-A architecture provides access to 64-bit wide integer registers and data operations, and the ability to use 64-bit sized pointers to memory. Armv8-A also includes the original Arm instruction set, now called A32.
Advanced features in Arm DynamIQ Cortex-A Processors
Cortex-A processors utilize multi-core technology to enables scalability from single up to four cores for traditional MPCore processors, and single up to eight cores for DynamIQ processors - this enables higher amounts of compute processing to take place within the CPU system. Multicore processing provides the ability for any of the four component processors, within a cluster, to shut down when not in use, for instance when the device is in standby mode, to save power. When higher performance is required, every processor is in use to meet the demand while still sharing the workload to keep power consumption as low as possible. Processors based on DynamIQ also improve on data security and privacy, advanced safety and RAS features, and integrated AI capabilities that enable DynamIQ-based systems to deliver a wide range of solutions. Advanced power management features integrated into the DynamIQ processors deliver higher amounts of power savings for energy-efficient designs.
Intelligent compute capabilities
Cortex-A CPUs that are designed based on DynamIQ technology can carry out advanced compute capabilities in Machine Learning and Artificial Intelligence.
Interfaces for closely coupled accelerators
DynamIQ technology provides the ability to closely couple Cortex-A CPUs with external accelerators and I/O-coherent IP, delivering up to 10x faster response times between CPU and specialized accelerator hardware on the SoC, compared to traditional clusters. This enables DynamIQ-based systems to carry out offload acceleration and I/O-coherent processing for applications such as cryptography acceleration and packet processing with higher performance and lower latency.
Built-in power-saving features
DynamIQ comes integrated with a host of new power management solutions. A more rapid and autonomous hardware-controlled power state transition mechanism reduces the latency between the power states supported by Arm Cortex-A CPUs, for example ON, OFF, and SLEEP. It also includes an autonomous CPU memory power solution, which intelligently adapts the amount of local memory available to the CPUs depending on the type of application running.
Additionally, DynamIQ technology enables finer-grained Dynamic Voltage and Frequency Scaling (DVFS) of individual and groups of CPUs in a DynamIQ cluster. This maximizes the achieved performance in devices that have a fixed thermal budget, while also providing more power savings from all applications of the technology.
Next-generation big.LITTLE Cortex-A CPU clusters can now be designed with a combination of high performance ‘big’ CPUs and high efficiency ‘LITTLE’ CPUs in one cluster, with a shared coherent memory. DynamIQ big.LITTLE delivers significant improvements in performance gained from a tighter, more coherent system. It also presents unprecedented flexibility and new choices in CPU topology, such as 1xbig + 7xLITTLE, to deliver purpose-built solutions.
Advanced RAS and safety features
DynamIQ processors support higher levels of safety requirements such as ASIL D and SIL-3. All DynamIQ-based IP are taken through a rigorous design flow to avoid systematic faults. Additionally, safety-related application performance is improved with shorter latency in decision making and actuation across AI scenarios such as Advanced Driver Assistance Systems (ADAS) for autonomous vehicles. DynamIQ based systems also come integrated with advanced features that improve Reliability, Availability and Serviceability (RAS) for applications such as industrial and infrastructure.