Cortex-A Series Characteristics
All ARMv7-A and ARMv8-A based processor cores featured in the current ARM Processor Portfolio support ARM's multicore technologies.
- Single to quad-core implementation for performance orientated applications
- Supports symmetric and asymmetric OS implementations
- Coherency throughout the processor exported to system via Accelerator Coherency Port (ACP)
The big.LITTLE compatible processors extend multi-core coherence beyond the 1-4 core clusters with AMBA® 4 ACE (AMBA Coherency Extension) and AMBA 5 CHI (Coherent Hub Interface).
A number of key points are common to the Cortex-A family of devices:
- 32-bit RISC core, with 16 × 32-bit visible registers with mode-based register banking
- Modified Harvard Architecture (separate, concurrent access to instructions and data)
- Load/Store Architecture
- Thumb-2 technology as standard
- VFP and NEON options
- Backward compatibility with code from previous ARM processors
- 4GB of virtual address space and a minimum of 4GB of physical address space
- Hardware translation table walking for virtual to physical address translation
- Virtual page sizes of 4KB, 64KB, 1MB and 16MB. Cacheability attributes and access permissions can be set on a per-page basis
- Big-endian and little-endian data access support
- Unaligned access support for basic load/store instructions
- Symmetric Multi-processing (SMP) support on MPCore™ variants, that is, multi-core versions of the Cortex-A series processors, with full data coherency at the L1 cache level. Automatic cache and Translation Lookaside Buffer (TLB) maintenance propagation provides high efficiency SMP operation
Cortex-A Series Programmer's Guide for ARMv7-A
Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for ARMv7-A.Get the Guide
Cortex-A Series Programmer's Guide for ARMv8-A
Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for ARMv8-A.Programmer's Guide for ARMv8-A
Porting to ARM 64-bit
If you are migrating from an ARMv7 architecture based design to the ARMv8 64-bit A64 instruction set, we provide a porting guide to help you.Porting to ARM 64-bit
Development Tools for Cortex-A
ARM and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.Development Tools
Cortex-A Safety Documents Package
For customers who needs to safety certify their end products, ARM provides a Safety Documentation Package for silicon developers and safety certified toolchain to accelerate the time to market.
ARMv8-A ArchitectureARMv8-A architecture provides access to 64-bit wide integer registers and data operations, and the ability to use 64-bit sized pointers to memory. ARMv8-A also includes the original ARM instruction set, now called A32.
Advanced Multi-Core Features in ARM Cortex-A Processors
The Cortex-A processors also utilize the widely established ARM MPCore multicore technology, enabling performance scalability and control over power consumption to exceed the performance of today's comparable high-performance devices while remaining within tight mobile power constraints. Multicore processing provides the ability for any of the four component processors, within a cluster, to shut down when not in use, for instance when the device is in standby mode, to save power. When higher performance is required, every processor is in use to meet the demand while still sharing the workload to keep power consumption as low as possible.
Snoop Control Unit (SCU)
The SCU is responsible for managing the interconnect, arbitration, communication, cache to cache and system memory transfers, cache coherence and other capabilities for the processor. ARM Cortex-A processors may also expose these capabilities to other system accelerators and non-cached DMA driven peripherals to increase performance and reduce system wide power consumption. This system coherence also reduces software complexity involved in maintaining software coherence within each OS driver.
Accelerator Coherence Port
This AMBA 4 AXI compatible slave interface on the SCU provides an interconnect point for masters that are interfaced directly with a Cortex-A processor. This interface supports all standard read and write transactions without additional coherence requirements. However, any read transactions to a coherent region of memory will interact with the SCU to test whether the information is already stored in the L1 caches. The SCU will enforce write coherence before the write is forwarded to the memory system and may allocate into the L2 cache, removing the power and performance impact of writing directly to off chip memory.
Generic Interrupt Controller (GIC)
Implementing the standardized and architected interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritization of system interrupts. Supporting up to 224 independent interrupts, under software control, each interrupt can be distributed across CPU, hardware prioritized, and routed between the operating system and TrustZone software management layer. This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a hypervisor.