Cortex-A75

The Arm Cortex-A75 processor is Arm's latest and highest-performance application CPU delivering ground-breaking performance and market-leading power efficiency across a wide range of applications. 

Information on Cortex-A75.

Getting Started

Performance from edge to cloud

The Arm Cortex-A75 CPU is built on DynamIQ technology, enabling new levels of scalability and responsiveness for your advanced use cases. 

The processor is broadly applicable from cloud to edge, providing improvements in performance, efficiency, and architecture over its predecessors, the Cortex-A72 and Cortex-A73 processors. With significantly improved integer performance, and substantial enhancements in floating point and memory workloads performance, the Cortex-A75 processor is the most powerful Cortex-A processor to date.

This additional compute capability, combined with improvements for machine learning and other advanced use cases, will enable demanding applications to run more smoothly and provide a new baseline for even more complex workloads to be developed.

Learn more about Arm DynamIQ technology.


Specifications

General Architecture Armv8-A (Harvard)
  Extensions Armv8.1 extensions,
Armv8.2 extensions,
Cryptography extensions,
RAS extensions,
Armv8.3 (LDAPR instructions only)
  ISA Support A64, A32, and T32 instruction sets 
Microarchitecture Pipeline Out-of-order
  Superscalar Yes
  Neon / Floating Point Unit  Included
  Cryptography Unit
Optional
  Max Number of CPUs in Cluster Four (4)
  Physical Addressing (PA) 44-bit
Memory System and External Interfaces L1 I-Cache / D-Cache 64KB
  L2 Cache 256KB to 512KB 
  L3 Cache Optional 512KB to 4MB
  ECC Support Yes 
  LPAE Yes 
  Bus Interfaces ACE or CHI 
  ACP Optional 
  Peripheral Port Optional 
Other Functional Safety Support Safety package
  Security TrustZone 
  Interrupts GIC Interface, GICv4 
  Generic Timer  Armv8-A
  PMU PMUv3 
  Debug Armv8-A (plus Armv8.2-A extensions) 
  CoreSight CoreSightv3 
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

  • Manual containing technical information.
  • The Cortex-A75 Technical Reference Manual

    For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
  • A guide on software optimization.
  • Cortex-A Series Programmer’s Guide to Armv8.2-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for
    Armv8.2-A.

    Coming Soon

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A75 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Not answered How can I get the Fast Models license 0 votes 0 views 0 replies Started 6 hours ago by Terry Chan Answer this
Suggested answer Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped
  • Cortex-A9
  • CoreLink L2C-310 Level 2 Cache Controller
0 votes 310 views 4 replies Latest 7 hours ago by teamrtos Answer this
Suggested answer How to start with Cortex-M1
  • cortex-m1
0 votes 44 views 1 replies Latest 16 hours ago by Joseph Yiu Answer this
Suggested answer Arm keil4 optimization 0 votes 56 views 1 replies Latest 16 hours ago by Joseph Yiu Answer this
Suggested answer M0 Synthesis Power Report
  • Cortex-M0
  • DesignStart
0 votes 48 views 1 replies Latest 16 hours ago by Joseph Yiu Answer this
Suggested answer Cortex-M3 DEBUG with CMSIS-DAP trouble 0 votes 0 views 1 replies Latest 18 hours ago by Joseph Yiu Answer this
Not answered How can I get the Fast Models license Started 6 hours ago by Terry Chan 0 replies 0 views
Suggested answer Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped Latest 7 hours ago by teamrtos 4 replies 310 views
Suggested answer How to start with Cortex-M1 Latest 16 hours ago by Joseph Yiu 1 replies 44 views
Suggested answer Arm keil4 optimization Latest 16 hours ago by Joseph Yiu 1 replies 56 views
Suggested answer M0 Synthesis Power Report Latest 16 hours ago by Joseph Yiu 1 replies 48 views
Suggested answer Cortex-M3 DEBUG with CMSIS-DAP trouble Latest 18 hours ago by Joseph Yiu 1 replies 0 views