Cortex-A15 Overview

The Cortex-A15 processor is a high-performance processor that implements the ARMv7-A architecture, which can be paired with the Cortex-A7 processor in a big.LITTLE configuration for mobile applications. The Cortex-A15 processor cluster has one to four cores, each with their L1 instruction and data caches, together with a single shared L2 unified cache.

  • Cortex-A15 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Technical Reference Manual
  • Cortex-A Series Programmer's Guide for ARMv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for ARMv7-A.

    Get the Guide
  • Development Tools for Cortex-A

    ARM and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools


Architecture ARMv7-A
Multicore 1-4x Symmetric Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters using AMBA® 4 ACE technology. Compatible with CCI-400 for up to two clusters, CCN-504 for up to four clusters, and a large level 3 cache for optimal performance
ISA Support
  • ARMv7-A
  • Thumb®-2
  • TrustZone® security technology
  • NEON™ Advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 Floating point
  • Hardware virtualization support
  • Large Physical Address Extensions (LPAE)
  • Integer Divide
  • Fused MAC
  • Hypervisor debug instructions
Memory Management Unit (MMU) ARMv7 Memory Management Unit
Debug & Trace CoreSight™ SoC

Key Features

Out-of-Order Pipeline

ARM’s highest performance 32-bit triple-issue out-of-order pipeline which removes code dependencies to achieve high peak and sustained instruction throughputs.

Virtualisation Support

ARM’s first ARMv7-A core with the Cortex-A7 big.LITTLE companion to provide hardware virtualisation support enabling sharing of hardware resources across multiple virtualised compute domains.

Cost-Effective / High-Performance

50% performance improvement over the Cortex-A9, 20% lower than Cortex-A57, with an option to significantly reduce area with the removal of the Neon/VFP SIMD unit.

Infrastructure Features

Support for networking and storage application with full ECC cache and 40-bit addressing up to 1TB.
Cortex-A15 Performance Relative to Cortex-A9

Cortex-A15 Performance Relative to Cortex-A9

Cortex-A15 Characteristics

The Cortex-A15 features a highly out-of-order processing engine with a 15 stage pipeline. This enables it to meet the requirements of modern day mobile computing where it must meet two opposite targets; high responsiveness or frame rate for gaming and web surfing, alongside maximizing the battery life to deliver an untethered user experience.

In a single-core configuration, the Cortex-A15 processor can achieve greater performance than the Cortex-A9 processor in key functions. This makes the processor ideal for devices which have rich functionality or need to execute functions at high speeds.

In order for devices to meet both targets simultaneously, ARM has invented big.LITTLE technology. By offering a ‘right core for the right task’ solution, devices can benefit from impressive power savings. ARM’s big.LITTLE technology assigns background and light tasks to the “LITTLE” core and the primary larger tasks to the “big” core. Not only does this allow the larger core to operate more efficiently as it is not trying to continuously context switch to cover the light threads, the consumer benefits from greatly increased battery life alongside top-end performance that can be greater than an individual Cortex-A15 core.

The Cortex-A15 processor can be implemented in a single or multicore configuration and can be paired with the Cortex-A7 to enable big.LITTLE configurations. This means that the processor provides a range of solutions for different use cases.