Cortex-A15

The Cortex-A15 is a high-performance processor that implements the Armv7-A architecture.

Cortex A15 chip diagram

Getting Started

The Cortex-A15 has enjoyed proven success, with shipments in excess of 50 million units across a variety of smartphones and infrastructure applications. The processor cluster has one to four cores. Each core has its own L1 instruction and data caches, together with a single shared L2 unified cache.


Specifications

Architecture Armv7-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 ACE technology. Compatible with CCI-400 for up to two clusters, CCI-504 for up to four clusters, and a large level 3 cache for optimal performance.
ISA Support
 
  • Armv7-A
  • Thumb-2
  • TrustZone security technology
  • NEON Advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 Floating point
  • Hardware virtualization support
  • Large Physical Address Extensions (LPAE)
  • Integer Divide
  • Fused MAC
  • Hypervisor debug instructions
Memory Management Unit (MMU)
Armv7 Memory Management Unit
Debug & Trace
CoreSight

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Characteristics

The Cortex-A15 features a highly out-of-order processing engine with a 15 stage pipeline. This enables it to meet the requirements of modern day mobile computing where it must meet two opposite targets; high responsiveness or frame rate for gaming and web surfing, alongside maximizing the battery life to deliver an untethered user experience.

In a single-core configuration, the Cortex-A15 processor can achieve greater performance than the Cortex-A9 processor in key functions. This makes the processor ideal for devices which have rich functionality or need to execute functions at high speeds.

In order for devices to meet both targets simultaneously, Arm has invented big.LITTLE technology. By offering a ‘right core for the right task’ solution, devices can benefit from impressive power savings. Arm’s big.LITTLE technology assigns background and light tasks to the “LITTLE” core and the primary larger tasks to the “big” core. Not only does this allow the larger core to operate more efficiently as it is not trying to continuously context switch to cover the light threads, the consumer benefits from greatly increased battery life alongside top-end performance that can be greater than an individual Cortex-A15 core.

The Cortex-A15 processor can be implemented in a single or multicore configuration and can be paired with the Cortex-A7 to enable big.LITTLE configurations. This means that the processor provides a range of solutions for different use cases.


  • Manual containing technical information.
  • Cortex-A15 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A15 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-A15 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A15 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Mali-450 GPU

Mali Display Processors

Mali-V500 Video-Processor

CoreLink Cache Coherent Interconnect Family

Memory Controllers

CoreLink System Controllers

Interrupt Controllers

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

 

Community Blogs

Community Forums

Answered Whether Armv7-A has a Write Buffer 0 votes 208 views 8 replies Latest 19 hours ago by Yang Wang Answer this
Answered dsb and dmb 0 votes 988 views 11 replies Latest 2 days ago by digital_kevin Answer this
Answered Armv7 Store Buffer 0 votes 271 views 6 replies Latest 3 days ago by Yang Wang Answer this
Answered Digital design flow (synthesis) 0 votes 543 views 5 replies Latest 4 days ago by Joseph Yiu Answer this
Answered A panic function to halt the processor in low-power sleep using WFI? 1 votes 263 views 5 replies Latest 4 days ago by 42Bastian Schick Answer this
Answered SAU, IDAU, MPC and PPC. What's the difference?
  • Musca-A
  • TrustZone for Armv8-M
  • TrustZone
  • Cortex-M33
2 votes 196 views 2 replies Latest 5 days ago by Afonso Santos Answer this
Answered Whether Armv7-A has a Write Buffer Latest 19 hours ago by Yang Wang 8 replies 208 views
Answered dsb and dmb Latest 2 days ago by digital_kevin 11 replies 988 views
Answered Armv7 Store Buffer Latest 3 days ago by Yang Wang 6 replies 271 views
Answered Digital design flow (synthesis) Latest 4 days ago by Joseph Yiu 5 replies 543 views
Answered A panic function to halt the processor in low-power sleep using WFI? Latest 4 days ago by 42Bastian Schick 5 replies 263 views
Answered SAU, IDAU, MPC and PPC. What's the difference? Latest 5 days ago by Afonso Santos 2 replies 196 views