Cortex-A17

The Arm Cortex-A17 processor is the highest performance Armv7-A processor.

Getting Started

The Arm Cortex-A17 processor offers 60% more single thread performance over the Cortex-A9 in a power and area-efficient package, which makes it ideal for mid-range solutions. The processor includes the latest Armv7-A features such as virtualization support, Large Physical Addressing Extension (LPAE), NEON and 128-bit ACE interface.

Information on Cortex-A17.

Key benefits

  • Highest performance for Armv7-A software ecosystem.

  • Cost efficiency with premium 32-bit performance for mass-market devices.

  • Mature and shipped in a wide range of consumer and embedded markets.

Specifications

Architecture Armv7-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 ACE technology. Compatible with CCI-400 for up to two clusters.
ISA Support
 
  • Arm and Thumb-2
  • TrustZone security technology
  • NEON Advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 Floating point
  • Hardware virtualization support
  • Large Physical Address Extensions (LPAE)
  • Integer Divide
  • Fused MAC
  • Hypervisor debug instructions
Memory Management Unit (MMU)
Armv7 Memory Management Unit
Debug & Trace
CoreSight

Looking for more information on Arm Cortex-A17

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Characteristics

 The Cortex-A17 processor is optimized for maximum performance for mobile mid-range power budgets. With 60% more single thread performance over the Cortex-A9 processor, the Cortex-A17 processor is the fastest mid-range solution available.

Additionally, the Cortex-A17 processor offers 50% performance uplift over Cortex-A9 on NEON and FPU workloads, boosting performance of any code leveraging this capability such as audio and video codecs.

With expected frequencies beyond 2.5GHz in 28nm, the Cortex-A17 processor can be scaled in size to meet a range of different application demands. Topologies are expected to vary depending on the use case due to the malleability of the Cortex-A17 processor.

  • Manual containing technical information.
  • Cortex-A17 Technical Reference Manual

    The complete guide for system designers, integrators and programmers working on Cortex-A17 based System-on-Chips.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Learn more

Related IP

The Cortex-A17 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A17 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Mali-450 GPU

Mali Display Processors

Mali-V500 Video Processor

CoreLink Interconnect

Interrupt Controllers

CoreLink System Controllers

CoreLink DMC-500 and CoreLink DMC-520

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

 

  • Product due to be released to  market.
  • Arm Design Reviews

    Arm's on-site design review service gives licensees confidence that their Cortex-A17 CPU is implemented efficiently, to provide maximum system performance, with lowest risk and fastest time-to-market.

    Learn more
  • The top half of a human.
  • Questions? Request more information

    Learn more about Cortex-A17, the Cortex-A17 processor is the highest performance Armv7-A processor. Contact us to speak with our technical team.


    Find out more

Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A17 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses Arm Design Reviews

Community Blogs

Community Forums

Telligent.Forums.NotAnswered Push/Pop in Cortex A55 64bit mode
  • Cortex-A55
0 Telligent.Forums.Votes 20 Telligent.Forums.Views 0 Telligent.Forums.Replies Telligent.Forums.Started 20 hours ago Telligent.Forums.By PrabhuKrishnan Telligent.Forums.AnswerThis
Telligent.Forums.Answered Barrier after access to memory mapped register?
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  • AArch64
0 Telligent.Forums.Votes 1196 Telligent.Forums.Views 9 Telligent.Forums.Replies Telligent.Forums.Latest yesterday Telligent.Forums.By dedoz Telligent.Forums.AnswerThis
Telligent.Forums.NotAnswered How to connect a ST-Link debugger to a Cortex-M1 design
  • xilinx
  • cortex-m1
  • Keil
  • DesignStart
  • debugger
0 Telligent.Forums.Votes 36 Telligent.Forums.Views 0 Telligent.Forums.Replies Telligent.Forums.Started 2 days ago Telligent.Forums.By Matic Obid Telligent.Forums.AnswerThis
Telligent.Forums.NotAnswered Write to flash memory with Trustzone active (armv8-M33)
  • Arm
  • trustzone for armv8-m
  • stm32
  • TrustZone
  • Cortex-M33
0 Telligent.Forums.Votes 139 Telligent.Forums.Views 0 Telligent.Forums.Replies Telligent.Forums.Started 4 days ago Telligent.Forums.By Simon Telligent.Forums.AnswerThis
Telligent.Forums.SuggestedAnswer Pipeline and Reorder Buffer on Cortex A9 0 Telligent.Forums.Votes 115 Telligent.Forums.Views 1 Telligent.Forums.Replies Telligent.Forums.Latest 5 days ago Telligent.Forums.By a.surati Telligent.Forums.AnswerThis
Telligent.Forums.NotAnswered Internal Authenticate command about PL131 0 Telligent.Forums.Votes 66 Telligent.Forums.Views 0 Telligent.Forums.Replies Telligent.Forums.Started 7 days ago Telligent.Forums.By fgvffvvfg Telligent.Forums.AnswerThis
Telligent.Forums.NotAnswered Push/Pop in Cortex A55 64bit mode Telligent.Forums.Started 20 hours ago Telligent.Forums.By PrabhuKrishnan 0 Telligent.Forums.Replies 20 Telligent.Forums.Views
Telligent.Forums.Answered Barrier after access to memory mapped register? Telligent.Forums.Latest yesterday Telligent.Forums.By dedoz 9 Telligent.Forums.Replies 1196 Telligent.Forums.Views
Telligent.Forums.NotAnswered How to connect a ST-Link debugger to a Cortex-M1 design Telligent.Forums.Started 2 days ago Telligent.Forums.By Matic Obid 0 Telligent.Forums.Replies 36 Telligent.Forums.Views
Telligent.Forums.NotAnswered Write to flash memory with Trustzone active (armv8-M33) Telligent.Forums.Started 4 days ago Telligent.Forums.By Simon 0 Telligent.Forums.Replies 139 Telligent.Forums.Views
Telligent.Forums.SuggestedAnswer Pipeline and Reorder Buffer on Cortex A9 Telligent.Forums.Latest 5 days ago Telligent.Forums.By a.surati 1 Telligent.Forums.Replies 115 Telligent.Forums.Views
Telligent.Forums.NotAnswered Internal Authenticate command about PL131 Telligent.Forums.Started 7 days ago Telligent.Forums.By fgvffvvfg 0 Telligent.Forums.Replies 66 Telligent.Forums.Views