Cortex-A17 Technical Reference ManualThe complete guide for system designers, integrators and programmers working on Cortex-A17 based System-on-Chips.
Technical Reference Manual
Cortex-A Series Programmer's Guide for ARMv7-A
Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for ARMv7-A.Get the Guide
Development Tools for Cortex-A
ARM and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.Development Tools
|Multicore||1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters using AMBA 4 ACE technology. Compatible with CCI-400 for up to two clusters.|
|Memory Management Unit (MMU)||ARMv7 Memory Management Unit|
|Debug & Trace||CoreSight™ SoC|
Out-of-order 11+ stage pipelineFully out-of-order pipeline with increased issuing capabilities for higher performance. It includes a 128-bit data path.
Integrated and configurable L2 Cache ControllerProvides low-latency and high-bandwidth access to up to 8MB of cached memory in high-frequency designs.
Support ARMv7-A extensions
Hardware Virtualization and Large Physical Address Extensions (LPAE) enables the processor to access up to 1TB of memory.
Architecturally compatible with Cortex-A7 for an efficient big.LITTLE system using ARM CCI interconnect.
Cortex-A17 Performance Relative to Cortex-A9
The Cortex-A17 processor is optimized for maximum performance for mobile mid-range power budgets. With 60% more single thread performance over the Cortex-A9 processor, the Cortex-A17 processor is the fastest mid-range solution available.
Additionally, the Cortex-A17 processor offers 50% performance uplift over Cortex-A9 on NEON and FPU workloads, boosting performance of any code leveraging this capability such as audio and video codecs.
With expected frequencies beyond 2.5GHz in 28nm, the Cortex-A17 processor can be scaled in size to meet a range of different application demands. Topologies are expected to vary depending on the use case due to the malleability of the Cortex-A17 processor.