Cortex-A17

The Arm Cortex-A17 processor is the highest performance Armv7-A processor.

Cortex-A17 chip diagram

Getting Started

The Arm Cortex-A17 processor offers 60% more single thread performance over the Cortex-A9 in a power and area-efficient package, which makes it ideal for mid-range solutions. The processor includes the latest Armv7-A features such as virtualization support, Large Physical Addressing Extension (LPAE), Neon and 128-bit ACE interface.


Specifications

Architecture Armv7-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 ACE technology. Compatible with CCI-400 for up to two clusters.
ISA Support
 
  • Arm and Thumb-2
  • TrustZone security technology
  • Neon Advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 Floating point
  • Hardware virtualization support
  • Large Physical Address Extensions (LPAE)
  • Integer Divide
  • Fused MAC
  • Hypervisor debug instructions
Memory Management Unit (MMU)
Armv7 Memory Management Unit
Debug & Trace
CoreSight

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Characteristics

 The Cortex-A17 processor is optimized for maximum performance for mobile mid-range power budgets. With 60% more single thread performance over the Cortex-A9 processor, the Cortex-A17 processor is the fastest mid-range solution available.

Additionally, the Cortex-A17 processor offers 50% performance uplift over Cortex-A9 on Neon and FPU workloads, boosting performance of any code leveraging this capability such as audio and video codecs.

With expected frequencies beyond 2.5GHz in 28nm, the Cortex-A17 processor can be scaled in size to meet a range of different application demands. Topologies are expected to vary depending on the use case due to the malleability of the Cortex-A17 processor.

  • Manual containing technical information.
  • Cortex-A17 Technical Reference Manual

    The complete guide for system designers, integrators and programmers working on Cortex-A17 based System-on-Chips.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Learn more

Get Support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A17 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-A17 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A17 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Mali-450 GPU

Mali Display Processors

Mali-V500 Video Processor

CoreLink Interconnect

Interrupt Controllers

CoreLink System Controllers

CoreLink DMC-500 and CoreLink DMC-520

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

 


Community Blogs

Community Forums

Not answered Neoverse N1 CPU Questions 0 votes 96 views 0 replies Started 23 hours ago by Riccardo89 Answer this
Not answered Fundamental Doubt in AHB Bus Architecture
  • Protocols
  • SoC Implementation
  • Interface Bus Architecture
  • Networking Protocol
  • ahb-lite
  • microcontroller
0 votes 27 views 0 replies Started 23 hours ago by Kedhar Guhan Answer this
Suggested answer M0+ Stack Pointer (PSP/MSP) Clarification
  • Cortex-M0
  • R13 (SP Stack Pointer)
  • cortex-m0+
0 votes 581 views 14 replies Latest yesterday by Sean Dunlevy Answer this
Answered Using uVision Eval version with Xilinx DesignStart examples 0 votes 79 views 1 replies Latest yesterday by Sean Houlihane Answer this
Answered ARMv8-A: Virtual to physical translation sometime "fails"
  • Armv8-A
0 votes 85 views 1 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped
  • Cortex-A9
  • CoreLink L2C-310 Level 2 Cache Controller
0 votes 453 views 6 replies Latest yesterday by teamrtos Answer this
Not answered Neoverse N1 CPU Questions Started 23 hours ago by Riccardo89 0 replies 96 views
Not answered Fundamental Doubt in AHB Bus Architecture Started 23 hours ago by Kedhar Guhan 0 replies 27 views
Suggested answer M0+ Stack Pointer (PSP/MSP) Clarification Latest yesterday by Sean Dunlevy 14 replies 581 views
Answered Using uVision Eval version with Xilinx DesignStart examples Latest yesterday by Sean Houlihane 1 replies 79 views
Answered ARMv8-A: Virtual to physical translation sometime "fails" Latest yesterday by 42Bastian Schick 1 replies 85 views
Suggested answer Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped Latest yesterday by teamrtos 6 replies 453 views