Cortex-A5

The Cortex-A5 processor is the smallest, lowest power Armv7 application processor.

Information on Cortex-A5.

Getting Started

The Cortex-A5 is the smallest and lowest power applications processor, delivering rich functionality to high-performance, power-sensitive devices.


Key benefits

  • The smallest application processor designed by Arm with uniprocessor (UP) and multiprocessor (MP) licensing options.

  • Configurable processor with optional NEON, optional FPU, and L1 cache configurable from 4K-64KB.

  • Full feature set of Cortex-A9 processor at one third the area and power.

Characteristics & Related IP

The Cortex-A5 is the smallest and lowest power applications processor, delivering rich functionality to high-performance, power-sensitive devices.

The processor’s small physical size also means reduced manufacturing costs, reduced system leakage and increased low-cost integration. Compared to the Cortex-A9 processor, the Cortex-A5 achieves more than 50% power efficiency while maintaining around 70-75% of the same performance level, making it ideal for wearable technology.

The Cortex-A5 processor is designed to be a highly configurable processor. The instruction and data cache sizes, for example, can be configured from a 64KB maximum size to as small as 4KB for cost-sensitive applications requiring a small application processor with a Memory Management Unit (MMU).

The Cortex-A5 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A5 processor is fully supported by Arm development tools. Related IP includes:


Graphic IP
Other IP
Tools

Mali-400 GPU

CoreLink Network Interconnect Family

CoreLink System Controllers

Interrupt Controllers

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

 

The Cortex-A5 also offers other configurability options such as optional Floating-Point Unit (FPU) and NEON which enable designers to make trade-offs for performance and cost in their targeted application. In its smallest possible configuration with 4KB caches, the Cortex-A5 can be just 0.2mm2 in size at 28nm process technology.


  • Manual containing technical information.
  • Cortex-A5 Technical Reference Manual

    The main resource for hardware and software engineers implementing the Cortex-A5 processor in system designs.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Learn more

Community Blogs

Community Forums

Telligent.Forums.NotAnswered Push/Pop in Cortex A55 64bit mode
  • Cortex-A55
0 Telligent.Forums.Votes 32 Telligent.Forums.Views 0 Telligent.Forums.Replies Telligent.Forums.Started yesterday Telligent.Forums.By PrabhuKrishnan Telligent.Forums.AnswerThis
Telligent.Forums.Answered Barrier after access to memory mapped register?
  • Cortex-A53
  • AArch64
0 Telligent.Forums.Votes 1218 Telligent.Forums.Views 9 Telligent.Forums.Replies Telligent.Forums.Latest 2 days ago Telligent.Forums.By dedoz Telligent.Forums.AnswerThis
Telligent.Forums.NotAnswered How to connect a ST-Link debugger to a Cortex-M1 design
  • xilinx
  • cortex-m1
  • Keil
  • DesignStart
  • debugger
0 Telligent.Forums.Votes 46 Telligent.Forums.Views 0 Telligent.Forums.Replies Telligent.Forums.Started 2 days ago Telligent.Forums.By Matic Obid Telligent.Forums.AnswerThis
Telligent.Forums.NotAnswered Write to flash memory with Trustzone active (armv8-M33)
  • Arm
  • trustzone for armv8-m
  • stm32
  • TrustZone
  • Cortex-M33
0 Telligent.Forums.Votes 148 Telligent.Forums.Views 0 Telligent.Forums.Replies Telligent.Forums.Started 4 days ago Telligent.Forums.By Simon Telligent.Forums.AnswerThis
Telligent.Forums.SuggestedAnswer Pipeline and Reorder Buffer on Cortex A9 0 Telligent.Forums.Votes 128 Telligent.Forums.Views 1 Telligent.Forums.Replies Telligent.Forums.Latest 5 days ago Telligent.Forums.By a.surati Telligent.Forums.AnswerThis
Telligent.Forums.NotAnswered Internal Authenticate command about PL131 0 Telligent.Forums.Votes 74 Telligent.Forums.Views 0 Telligent.Forums.Replies Telligent.Forums.Started 7 days ago Telligent.Forums.By fgvffvvfg Telligent.Forums.AnswerThis
Telligent.Forums.NotAnswered Push/Pop in Cortex A55 64bit mode Telligent.Forums.Started yesterday Telligent.Forums.By PrabhuKrishnan 0 Telligent.Forums.Replies 32 Telligent.Forums.Views
Telligent.Forums.Answered Barrier after access to memory mapped register? Telligent.Forums.Latest 2 days ago Telligent.Forums.By dedoz 9 Telligent.Forums.Replies 1218 Telligent.Forums.Views
Telligent.Forums.NotAnswered How to connect a ST-Link debugger to a Cortex-M1 design Telligent.Forums.Started 2 days ago Telligent.Forums.By Matic Obid 0 Telligent.Forums.Replies 46 Telligent.Forums.Views
Telligent.Forums.NotAnswered Write to flash memory with Trustzone active (armv8-M33) Telligent.Forums.Started 4 days ago Telligent.Forums.By Simon 0 Telligent.Forums.Replies 148 Telligent.Forums.Views
Telligent.Forums.SuggestedAnswer Pipeline and Reorder Buffer on Cortex A9 Telligent.Forums.Latest 5 days ago Telligent.Forums.By a.surati 1 Telligent.Forums.Replies 128 Telligent.Forums.Views
Telligent.Forums.NotAnswered Internal Authenticate command about PL131 Telligent.Forums.Started 7 days ago Telligent.Forums.By fgvffvvfg 0 Telligent.Forums.Replies 74 Telligent.Forums.Views