Cortex-A5

The Cortex-A5 processor is the smallest, lowest power Armv7 application processor.

Information on Cortex-A5.

Getting Started

The Cortex-A5 is the smallest and lowest power applications processor, delivering rich functionality to high-performance, power-sensitive devices.

DesignStart Pro

Fast, low-cost access to Cortex-A5 through Arm DesignStart.

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Specifications

Architecture Armv7-A
Multicore 1-4 cores
ISA Support
Memory Management Unit (MMU) Armv7 Memory Management Unit
Debug & Trace CoreSight

Characteristics

The Cortex-A5 is the smallest and lowest power applications processor, delivering rich functionality to high-performance, power-sensitive devices.

The processor’s small physical size also means reduced manufacturing costs, reduced system leakage and increased low-cost integration. Compared to the Cortex-A9 processor, the Cortex-A5 achieves more than 50% power efficiency while maintaining around 70-75% of the same performance level, making it ideal for wearable technology.

The Cortex-A5 processor is designed to be a highly configurable processor. The instruction and data cache sizes, for example, can be configured from a 64KB maximum size to as small as 4KB for cost-sensitive applications requiring a small application processor with a Memory Management Unit (MMU).

Performance comparison graph on Cortex-A5 and Cortex-A9.


  • Manual containing technical information.
  • Cortex-A5 Technical Reference Manual

    The main resource for hardware and software engineers implementing the Cortex-A5 processor in system designs.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Learn more

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Related IP

The Cortex-A5 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A5 processor is fully supported by Arm development tools. Related IP includes:

Graphic IP
Other IP
Tools

Mali-400 GPU

CoreLink Network Interconnect Family

CoreLink System Controllers

Interrupt Controllers

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

The Cortex-A5 also offers other configurability options such as optional Floating-Point Unit (FPU) and Neon which enable designers to make trade-offs for performance and cost in their targeted application. In its smallest possible configuration with 4KB caches, the Cortex-A5 can be just 0.2mm2 in size at 28nm process technology.

Community Blogs

Community Forums

Suggested answer setting brakpoint from code 0 votes 34 views 1 replies Latest 15 hours ago by 42Bastian Schick Answer this
Answered aarch64 Exception Level Sw itch from EL1 to EL0 0 votes 99 views 7 replies Latest 18 hours ago by michaelyuanfeng Answer this
Answered Looking for an eval board with octa core Armv8 CPU
  • AArch64
0 votes 276 views 7 replies Latest 18 hours ago by 42Bastian Schick Answer this
Not answered reference source code to verify the Cortex-R52
  • cortex-r52
  • Evaluation Boards
0 votes 26 views 0 replies Started yesterday by Jorney Answer this
Answered Exclusive Access Restriction Clarification
  • AMBA
0 votes 1483 views 4 replies Latest yesterday by Taniya Garg Answer this
Not answered when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot! 0 votes 34 views 0 replies Started yesterday by sam0220 Answer this
Suggested answer setting brakpoint from code Latest 15 hours ago by 42Bastian Schick 1 replies 34 views
Answered aarch64 Exception Level Sw itch from EL1 to EL0 Latest 18 hours ago by michaelyuanfeng 7 replies 99 views
Answered Looking for an eval board with octa core Armv8 CPU Latest 18 hours ago by 42Bastian Schick 7 replies 276 views
Not answered reference source code to verify the Cortex-R52 Started yesterday by Jorney 0 replies 26 views
Answered Exclusive Access Restriction Clarification Latest yesterday by Taniya Garg 4 replies 1483 views
Not answered when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot! Started yesterday by sam0220 0 replies 34 views