Cortex-A5

The Cortex-A5 processor is the smallest, lowest power Armv7 application processor.

Information on Cortex-A5.

Getting Started

The Cortex-A5 is the smallest and lowest power applications processor, delivering rich functionality to high-performance, power-sensitive devices.


Key benefits

  • The smallest application processor designed by Arm with uniprocessor (UP) and multiprocessor (MP) licensing options.

  • Configurable processor with optional NEON, optional FPU, and L1 cache configurable from 4K-64KB.

  • Full feature set of Cortex-A9 processor at one third the area and power.

Characteristics & Related IP

The Cortex-A5 is the smallest and lowest power applications processor, delivering rich functionality to high-performance, power-sensitive devices.

The processor’s small physical size also means reduced manufacturing costs, reduced system leakage and increased low-cost integration. Compared to the Cortex-A9 processor, the Cortex-A5 achieves more than 50% power efficiency while maintaining around 70-75% of the same performance level, making it ideal for wearable technology.

The Cortex-A5 processor is designed to be a highly configurable processor. The instruction and data cache sizes, for example, can be configured from a 64KB maximum size to as small as 4KB for cost-sensitive applications requiring a small application processor with a Memory Management Unit (MMU).

The Cortex-A5 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A5 processor is fully supported by Arm development tools. Related IP includes:


Graphic IP
Other IP
Tools

Mali-400 GPU

CoreLink Network Interconnect Family

CoreLink System Controllers

Interrupt Controllers

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

 

The Cortex-A5 also offers other configurability options such as optional Floating-Point Unit (FPU) and NEON which enable designers to make trade-offs for performance and cost in their targeted application. In its smallest possible configuration with 4KB caches, the Cortex-A5 can be just 0.2mm2 in size at 28nm process technology.


  • Manual containing technical information.
  • Cortex-A5 Technical Reference Manual

    The main resource for hardware and software engineers implementing the Cortex-A5 processor in system designs.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Learn more

Community Blogs

Community Forums

Discussion Please consider my tag for inclusion on the ARM Community 0 votes 14987 views 24 replies Latest 1 years ago by Hellen Norman Answer this
Answered Barrier after access to memory mapped register?
  • Cortex-A53
  • AArch64
0 votes 1236 views 9 replies Latest 4 days ago by dedoz Answer this
Answered How can I edit the community wiki?
  • ARM Community
0 votes 121 views 2 replies Latest 7 days ago by Ash Wilding Answer this
Discussion L2cache禁止,为什么cpu运行会比恒miss要慢?
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0 votes 4117 views 6 replies Latest 10 days ago by zhangyumao Answer this
Answered How to check the enable status in ETM v3.3
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  • Cortex-A8
0 votes 1686 views 3 replies Latest 16 days ago by Lorenzo_UR Answer this
Answered AXI protocol - Unaligned data transfer definition
  • AMBA
  • AXI
0 votes 3933 views 2 replies Latest 19 days ago by hayk Answer this
Discussion Please consider my tag for inclusion on the ARM Community Latest 1 years ago by Hellen Norman 24 replies 14987 views
Answered Barrier after access to memory mapped register? Latest 4 days ago by dedoz 9 replies 1236 views
Answered How can I edit the community wiki? Latest 7 days ago by Ash Wilding 2 replies 121 views
Discussion L2cache禁止,为什么cpu运行会比恒miss要慢? Latest 10 days ago by zhangyumao 6 replies 4117 views
Answered How to check the enable status in ETM v3.3 Latest 16 days ago by Lorenzo_UR 3 replies 1686 views
Answered AXI protocol - Unaligned data transfer definition Latest 19 days ago by hayk 2 replies 3933 views