- ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
- How to pause system level timers while CPU execution is halted
- Why are CoreSight debuggers unable to discover the memory-mapped Activity Monitor Unit (AMU) which does not have a CoreSight ROM table entry?
- The JTAG IDCODE for a Cortex processor
- Design Sign-off Model (DSM) does not function correctly in simulation.
- CoreTile Express A5x2 Technical Reference Manual
- Cortex-A5 Cycle Model User Guide
- Cortex-A5 Technical Reference Manual
- Cortex-A5 Floating-Point Unit Technical Reference Manual
- Cortex-A5 NEON Media Processing Engine Technical Reference Manual
- Software implications for v8-A implementations with no hardware floating point
- ARM C Language Extensions for SVE
For additional information search for Cortex-A5.