Cortex-A53

The Cortex-A53 processor is a high efficiency processor that implements the Armv8-A architecture. 

Getting Started

The Cortex-A53 processor has one to four cores, each with an L1 memory system and a single shared L2 cache. 

Specifications

Architecture  Armv8-A
 Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 technology
 ISA Support
  • AArch32 for full backward compatibility with Armv7
  • AArch64 for 64-bit support and new architectural features
  • TrustZone security technology
  • NEON advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 floating point
  • Hardware virtualization support
 Debug & Trace

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Characteristics

The Cortex-A53 processor delivers significantly more performance than its predecessors at a higher level of power efficiency. This takes the performance of the core above that of the Cortex-A7 processor, which defines many popular mainstream and entry-level mobile platforms. The performance graph to the right shows the performance improvements of the Cortex-A53 processor against the Cortex-A7 processor.

The Armv8-A architecture brings a number of new features. These include 64-bit data processing, extended virtual addressing and a 64-bit general purpose registers. The Cortex-A53 processor is Arm’s first Armv8-A processor aimed at providing power-efficient 64-bit processing. It features an in-order, 8-stage, dual-issue pipeline, and improved integer, NEON, Floating-Point Unit (FPU) and memory performance.

The Cortex-A53 can be implemented in two execution states: AArch32 and AArch64. The AArch64 state gives the Cortex-A53 its ability to execute 64-bit applications, while the AArch32 state allows the processor to execute existing Armv7-A applications.

  • Manual containing technical information.
  • Cortex-A53 Technical Reference Manual

    For system designers, system integrators and programmers who design SoC with Cortex-A53, the Technical Reference Manual is the go-to resource.

    Read here
  • Architecture A 62 guide
  • Porting to Arm 64-bit

    If you are migrating from an Armv7 architecture based design to the Armv8 64-bit A64 instruction set, we provide a porting guide to help you.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the guide

Related IP

The Cortex-A53 processor can be incorporated into a SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A53 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Mali-T860 and Mali-T880 GPUs

Mali-DP550 display processor

Mali-V550 video processor

CoreLink Interconnect

Interrupt Controllers

CoreLink System Controllers

Memory Controllers

 

DS-5 Development Studio

Fast Models

Development Boards

Arm Compiler

 

 
  • Product due to be released to  market.
  • Arm Design Reviews

    Arm's on-site design review service gives licensees confidence that their Cortex-A53 CPU is implemented efficiently, to provide maximum system performance, with lowest risk and fastest time-to-market.

    Learn more
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  • Questions? Request more information

    Learn more about Cortex-A53, Arm’s high efficiency processor that implements the Armv8-A architecture. Contact us to speak with our technical team.


    Find out more

Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A53 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses Arm Design Reviews

Community Blogs

Community Forums

Not answered Number of performance monitoring units in ARM Cortex A-53 and A-9
  • Cortex-A53
  • Cortex-A9
0 votes 36 views 0 replies Started yesterday by user Answer this
Suggested answer Push/Pop in Cortex A55 64bit mode
  • Cortex-A55
0 votes 72 views 1 replies Latest 2 days ago by 42Bastian Schick Answer this
Answered Barrier after access to memory mapped register?
  • Cortex-A53
  • AArch64
0 votes 1236 views 9 replies Latest 4 days ago by dedoz Answer this
Not answered How to connect a ST-Link debugger to a Cortex-M1 design
  • xilinx
  • cortex-m1
  • Keil
  • DesignStart
  • debugger
0 votes 58 views 0 replies Started 5 days ago by Matic Obid Answer this
Not answered Write to flash memory with Trustzone active (armv8-M33)
  • Arm
  • trustzone for armv8-m
  • stm32
  • TrustZone
  • Cortex-M33
0 votes 166 views 0 replies Started 7 days ago by Simon Answer this
Suggested answer Pipeline and Reorder Buffer on Cortex A9 0 votes 136 views 1 replies Latest 8 days ago by a.surati Answer this
Not answered Number of performance monitoring units in ARM Cortex A-53 and A-9 Started yesterday by user 0 replies 36 views
Suggested answer Push/Pop in Cortex A55 64bit mode Latest 2 days ago by 42Bastian Schick 1 replies 72 views
Answered Barrier after access to memory mapped register? Latest 4 days ago by dedoz 9 replies 1236 views
Not answered How to connect a ST-Link debugger to a Cortex-M1 design Started 5 days ago by Matic Obid 0 replies 58 views
Not answered Write to flash memory with Trustzone active (armv8-M33) Started 7 days ago by Simon 0 replies 166 views
Suggested answer Pipeline and Reorder Buffer on Cortex A9 Latest 8 days ago by a.surati 1 replies 136 views