The Arm Cortex-A55 processor is a market-leading CPU that delivers the best combination of power efficiency and performance in its class. It is part of the first generation of application CPUs based on DynamIQ technology and features the latest Armv8-A architecture extensions, with dedicated machine learning instructions.
The Cortex-A55 incorporates an extensively redesigned microarchitecture system that improves performance across the board while being very competitive in area and power efficiency. It delivers up to 18% more performance at 15% better power efficiency when compared to its predecessor, the Cortex-A53.
Designed to be an extremely scalable CPU, the versatile Cortex-A55 can be used to address a wide range of applications with diverging cost, from the edge to the cloud. The Cortex-A55 can be implemented in both stand-alone applications or as a ‘LITTLE’ CPU to the Cortex-A75 with DynamIQ big.LITTLE.
Armv8.3 (LDAPR instructions only)
|ISA Support||A64, A32, and T32 instruction sets|
|NEON / Floating Point Unit||Optional|
|Max Number of CPUs in Cluster||Eight (8)|
|Physical Addressing (PA)||40-bit|
|Memory System and External Interfaces||L1 I-Cache / D-Cache||16KB to 64KB
|L2 Cache||Optional, 64KB to 256KB|
|L3 Cache||Optional, 512KB to 4MB|
|Bus Interfaces||ACE or CHI|
|Other||Functional Safety Support||ASIL D systematic|
|Interrupts||GIC Interface, GICv4|
|Debug||Armv8-A (plus Armv8.2-A extensions)|
|Embedded Trace Macrocell||ETMv4.2 (instruction trace)
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The Cortex-A55 Technical Reference Manual
For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.Read here
Cortex-A55 Software Optimization Guide
For software engineers and programmers, the software optimization guide examines the performance characteristics of instructions in detail.Read here
Cortex-A Series Programmer’s Guide to Armv8.2-A
Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for
Cortex-A55 Safety Documents Package
For customers who needs to safety certification for their end products, Arm provides a Safety Documentation Package for silicon developers and safety-certified toolchain to accelerate the time to market.
Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A55 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Arm Design Reviews Open a support case
|Answered||Non-secure peripheral with a secure interrupt handler||0 votes||151 views||5 replies||Latest 8 hours ago by Joseph Yiu||Answer this|
|Suggested answer||HREADY when no activity on bus||0 votes||97 views||2 replies||Latest 11 hours ago by Tushar Valu||Answer this|
|Suggested answer||Store operations where the cache line is already cached (ACE protocol)||1 votes||119 views||1 replies||Latest 5 days ago by a.surati||Answer this|
|Answered||Whether Armv7-A has a Write Buffer||0 votes||505 views||8 replies||Latest 6 days ago by Yang Wang||Answer this|
|Suggested answer||Why AXI4 changed the definition of AxCACHE?||0 votes||160 views||1 replies||Latest 6 days ago by Colin Campbell||Answer this|
|Suggested answer||AXI read response in error case||0 votes||175 views||1 replies||Latest 7 days ago by Colin Campbell||Answer this|
|Answered||Non-secure peripheral with a secure interrupt handler Latest 8 hours ago by Joseph Yiu||5 replies 151 views|
|Suggested answer||HREADY when no activity on bus Latest 11 hours ago by Tushar Valu||2 replies 97 views|
|Suggested answer||Store operations where the cache line is already cached (ACE protocol) Latest 5 days ago by a.surati||1 replies 119 views|
|Answered||Whether Armv7-A has a Write Buffer Latest 6 days ago by Yang Wang||8 replies 505 views|
|Suggested answer||Why AXI4 changed the definition of AxCACHE? Latest 6 days ago by Colin Campbell||1 replies 160 views|
|Suggested answer||AXI read response in error case Latest 7 days ago by Colin Campbell||1 replies 175 views|