Cortex-A57 Overview

The Cortex-A57 processor is a high-performance processor that implements the ARMv8-A architecture, which can be paired with the Cortex-A53 processor in a big.LITTLE configuration for mobile applications. The Cortex-A57 processor cluster has one to four cores, each with their L1 instruction and data caches, together with a single shared L2 unified cache.

  • Cortex-A57 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource. Technical Reference Manual
  • Cortex-A Series Programmer's Guide for ARMv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for ARMv8-A.

    Programmer's Guide for ARMv8-A
  • Cortex-A57 Software Optimization Guide

    For software engineers and programmers, the software optimization guide examines the performance characteristics of instructions in detail.

    Optimization Guide
  • Development Tools for Cortex-A

    ARM and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools
  • Porting to ARM 64-bit

    If you are migrating from an ARMv7 architecture based design to the ARMv8 64-bit A64 instruction set, we provide a porting guide to help you.

    Porting to ARM 64-bit
  • Cortex-A Safety Documents Package

    For customers who needs to safety certify their end products, ARM provides a Safety Documentation Package for silicon developers and safety certified toolchain to accelerate the time to market.

Cortex-A57 Block Diagram


Architecture ARMv8-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 5 CHI or AMBA 4 ACE technology
ISA Support
  • AArch32 for full backward compatibility with ARMv7
  • AArch64 for 64-bit support and new architectural features
  • TrustZone security technology
  • NEON Advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 Floating point
  • Hardware virtualization support
Debug & Trace CoreSight DK-A57

Key Features

64-Bit Out-of-Order Pipeline

ARM’s first ARMv8-A 64-bit triple-issue out-of-order pipeline which removes code dependencies to achieve high peak and sustained instruction throughputs.

Prefetching Features

3X better memory streaming performance over Cortex-A15 with improvements in the speculative prefetching features.

Cryptography Extensions

3-10X performance improvement on software-based cryptography applications with the introduction of the Crypto acceleration unit.

Infrastructure Features

Support for networking and storage application with full ECC cache and 44-bit addressing up to 16TB.
Cortex-A57 Performance Improvement Relative to Cortex-A15

Cortex-A57 Performance Improvement Relative to Cortex-A15

Cortex-A57 Characteristics

The Cortex-A57 processor achieves high levels of performance through a range of microarchitectural implementations and an updated version of the ARM architecture. On the microarchitectural side, the processor features a highly out-of-order, multi-issue pipeline tuned for modern workloads with DSP and NEON™ SIMD extensions mandatory with each core. The inclusion of cryptography extensions improves performance on cryptography algorithms by 10 times over the current generation of processors. It delivers significantly more performance than the Cortex-A15, at a higher level of power efficiency.

The Cortex-A57 processor utilizes the ARMv8-A architecture, enabling power-efficient 64-bit support while maintaining compatibility with existing 32-bit software. As such, the architecture can run in two states. The AArch32 execution state runs existing ARM 32-bit applications while the AArch64 state executes applications in 64-bit code. The ability to provide 64-bit support significantly raises the performance level of the processor, and is ensuring that ARM continues to provide for next-generation devices requiring the right balance of power and performance.