Cortex-A57

The Cortex-A57 processor is a high-performance processor that implements the Armv8-A architecture, which can be paired with the Cortex-A53 processor in a big.LITTLE configuration for mobile applications. 

Information on Cortex-A57.

Getting Started

The Cortex-A57 processor cluster has one to four cores, each with their L1 instruction and data caches, together with a single shared L2 unified cache. 


Specifications

Architecture Armv8-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 5 CHI or AMBA 4 ACE technology
ISA Support
  • AArch32 for full backward compatibility with Armv7
  • AArch64 for 64-bit support and new architectural features
  • TrustZone security technology
  • Neon advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 floating point
  • Hardware virtualization support
Debug & Trace

  • A guide on software optimization.
  • Cortex-A57 Software Optimization Guide

    For software engineers and programmers, the Software Optimization Guide describes the performance characteristics of instructions in detail.

    Get the guide
  • Manual containing technical information.
  • Cortex-A57 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource. Technical Reference Manual

    Read here
  • Architecture A 62 guide
  • Porting to Arm 64-bit

    If you are migrating from an Armv7 architecture based design to the Armv8 64-bit A64 instruction set, we provide a porting guide to help you.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the guide
  • A manual that contains information on safety.
  • Cortex-A Safety Documents Package

    For customers who needs to safety certify their end products, Arm provides a Safety Documentation Package for silicon developers and safety certified toolchain to accelerate the time to market.

    Read here

Get Support

Arm Support

Arm training courses and Arm Design Reviews on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A57 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses    Arm Design Reviews  Open a support case

Related IP

The Cortex-A57 processor can be incorporated into a SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A57 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Mali-T860 and Mali-T880 GPUs

Mali-DP550 display processor

Mali-V550 video processor

CoreLink Cache Coherent Interconnect Family

CoreLink Interrupt Controllers

CoreLink System Controllers

CoreLink DMC-500

CoreLink DMC-520 

CoreSight SoC-400

POP IP (Physical IP)

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models 


Community Blogs

Community Forums

Suggested answer setting brakpoint from code 0 votes 28 views 1 replies Latest 14 hours ago by 42Bastian Schick Answer this
Answered aarch64 Exception Level Sw itch from EL1 to EL0 0 votes 98 views 7 replies Latest 17 hours ago by michaelyuanfeng Answer this
Answered Looking for an eval board with octa core Armv8 CPU
  • AArch64
0 votes 276 views 7 replies Latest 17 hours ago by 42Bastian Schick Answer this
Not answered reference source code to verify the Cortex-R52
  • cortex-r52
  • Evaluation Boards
0 votes 25 views 0 replies Started yesterday by Jorney Answer this
Answered Exclusive Access Restriction Clarification
  • AMBA
0 votes 1481 views 4 replies Latest yesterday by Taniya Garg Answer this
Not answered when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot! 0 votes 33 views 0 replies Started yesterday by sam0220 Answer this
Suggested answer setting brakpoint from code Latest 14 hours ago by 42Bastian Schick 1 replies 28 views
Answered aarch64 Exception Level Sw itch from EL1 to EL0 Latest 17 hours ago by michaelyuanfeng 7 replies 98 views
Answered Looking for an eval board with octa core Armv8 CPU Latest 17 hours ago by 42Bastian Schick 7 replies 276 views
Not answered reference source code to verify the Cortex-R52 Started yesterday by Jorney 0 replies 25 views
Answered Exclusive Access Restriction Clarification Latest yesterday by Taniya Garg 4 replies 1481 views
Not answered when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot! Started yesterday by sam0220 0 replies 33 views