Cortex-A57

The Cortex-A57 processor is a high-performance processor that implements the Armv8-A architecture, which can be paired with the Cortex-A53 processor in a big.LITTLE configuration for mobile applications. 

Information on Cortex-A57.

Getting Started

The Cortex-A57 processor cluster has one to four cores, each with their L1 instruction and data caches, together with a single shared L2 unified cache. 


Specifications

Architecture Armv8-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 5 CHI or AMBA 4 ACE technology
ISA Support
  • AArch32 for full backward compatibility with Armv7
  • AArch64 for 64-bit support and new architectural features
  • TrustZone security technology
  • NEON advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 floating point
  • Hardware virtualization support
Debug & Trace

  • A guide on software optimization.
  • Cortex-A57 Software Optimization Guide

    For software engineers and programmers, the Software Optimization Guide describes the performance characteristics of instructions in detail.

    Get the guide
  • Manual containing technical information.
  • Cortex-A57 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource. Technical Reference Manual

    Read here
  • Architecture A 62 guide
  • Porting to Arm 64-bit

    If you are migrating from an Armv7 architecture based design to the Armv8 64-bit A64 instruction set, we provide a porting guide to help you.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the guide
  • A manual that contains information on safety.
  • Cortex-A Safety Documents Package

    For customers who needs to safety certify their end products, Arm provides a Safety Documentation Package for silicon developers and safety certified toolchain to accelerate the time to market.

    Read here

Get Support

Arm Support

Arm training courses and Arm Design Reviews on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A57 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses    Arm Design Reviews  Open a support case

Related IP

The Cortex-A57 processor can be incorporated into a SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A57 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Mali-T860 and Mali-T880 GPUs

Mali-DP550 display processor

Mali-V550 video processor

CoreLink Cache Coherent Interconnect Family

CoreLink Interrupt Controllers

CoreLink System Controllers

CoreLink DMC-500

CoreLink DMC-520 

CoreSight SoC-400

POP IP (Physical IP)

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models 


Community Blogs

Community Forums

Suggested answer Store operations where the cache line is already cached (ACE protocol)
  • AMBA 4
1 votes 100 views 1 replies Latest 3 days ago by a.surati Answer this
Answered Whether Armv7-A has a Write Buffer 0 votes 474 views 8 replies Latest 4 days ago by Yang Wang Answer this
Suggested answer Why AXI4 changed the definition of AxCACHE?
  • AXI4
0 votes 145 views 1 replies Latest 5 days ago by Colin Campbell Answer this
Suggested answer AXI read response in error case 0 votes 154 views 1 replies Latest 5 days ago by Colin Campbell Answer this
Answered dsb and dmb 0 votes 1103 views 11 replies Latest 6 days ago by digital_kevin Answer this
Suggested answer DWT 0 votes 139 views 1 replies Latest 7 days ago by Joseph Yiu Answer this
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest 3 days ago by a.surati 1 replies 100 views
Answered Whether Armv7-A has a Write Buffer Latest 4 days ago by Yang Wang 8 replies 474 views
Suggested answer Why AXI4 changed the definition of AxCACHE? Latest 5 days ago by Colin Campbell 1 replies 145 views
Suggested answer AXI read response in error case Latest 5 days ago by Colin Campbell 1 replies 154 views
Answered dsb and dmb Latest 6 days ago by digital_kevin 11 replies 1103 views
Suggested answer DWT Latest 7 days ago by Joseph Yiu 1 replies 139 views