Cortex-A65AE

The Cortex-A65AE is a 64-bit multi-threaded Automotive Enhanced (AE) CPU with Split-Lock capability.

Getting started

The Cortex-A65AE is the first multi-threaded Cortex-A CPU for automotive applications. It is designed for devices undertaking high throughput and safety critical tasks. The Cortex-A65AE is built on DynamIQ technology and benefits from its resilient and flexible multicore features. It has also been designed with Dual Core Lock-Step (DCLS), an advanced feature for increased fault tolerance designs.

The Cortex-A65AE is part of Arm's Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development.

Key benefits

  • High throughput performance with dual-threaded, out-of-order execution
  • Split-Lock capability which offers the flexibility to operate in two modes; split mode for performance and lock mode for safety.
  • Fault-tolerant operation in lock mode with DCLS.

Key benefits compared to Cortex-A53:

  • 70% improved integer performance per core
  • 3.5x higher memory throughput for memory intensive automotive workloads
  • >6x higher read bandwidth on low-latency ACP for closely-coupled accelerators

Specifications

Architecture Armv8-A (Harvard)

 

Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 (LDAPR instructions only)
ISA support
  • A64

 

Microarchitecture Pipeline Out-of-order

 

Superscalar Yes

 

NEON/Floating Point Unit Included

 

Cryptography Unit Optional

 

Max number of CPUs in cluster Eight (8)

 

Physical Addressing (PA) 44-bit

 

Dual Core Lock-Step (DCLS) Yes (in safety-mode)
Memory system and external interfaces L1 I-Cache / D-Cache 16KB to 64KB

 

L2 Cache 64KB to 256KB

 

L3 Cache Optional, 512KB to 4MB

 

ECC Support Yes

 

LPAE Yes

 

Bus interfaces AMBA ACE or CHI

 

ACP Optional

 

Peripheral Port Optional
Other Functional Safety Support Supports ASIL D diagnostics

 

Security TrustZone

 

Interrupts GIC interface, GICv4

 

Generic timer Armv8-A

 

PMU PMUv3

 

Debug Armv8-A (plus Armv8.2-A extensions)

 

CoreSight CoreSightv3

 

Embedded Trace Macrocell ETMv4.2 (instruction trace)

Resources

Cortex-A Series Programmer's Guide for Armv8-A

Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

Development Tools for Cortex-A

Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

Get Support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A72 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

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Suggested answer Why AXI4 changed the definition of AxCACHE? Latest 8 hours ago by Colin Campbell 1 replies 67 views
Suggested answer Whether Armv7-A has a Write Buffer Latest 9 hours ago by vstehle 7 replies 127 views
Suggested answer AXI read response in error case Latest yesterday by Colin Campbell 1 replies 87 views
Answered dsb and dmb Latest yesterday by digital_kevin 11 replies 929 views
Suggested answer DWT Latest 2 days ago by Joseph Yiu 1 replies 73 views
Answered Armv7 Store Buffer Latest 2 days ago by Yang Wang 6 replies 252 views