Cortex-A7

The Arm Cortex-A7 processor is the most efficient Armv7-A processor.

Information on Cortex-A7.

Getting Started

The Cortex-A7 processor provides up to 20% more single thread performance than the Cortex-A5. The processor incorporates all features of the high-performance Cortex-A15 and Cortex-A17 processors, including virtualization support in hardware, Large Physical Address Extensions (LPAE), Neon, and 128-bit AMBA 4 AXI bus interface.


Specifications

Architecture Armv7-A
Multicore 1-4 cores. Symmetric Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 technology
ISA Support
  • Armv7-A
  • Thumb-2
  • TrustZone security technology
  • DSP extensions
  • Neon advanced SIMD
  • VFPv4 Floating Point
  • Hardware virtualization support
  • Large Physical Address Extensions (LPAE)
Memory Management Unit (MMU)
Armv7 Memory Management Unit
Debug & Trace
CoreSight

Characteristics

The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5 processor. It also benefits from an integrated L2 cache designed for low-power, with lower transaction latencies and improved OS support for cache maintenance. On top of this there is improved branch prediction and an improved memory system performance, with 64-bit load-store path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry, up from 128 entry for Cortex-A9 and Cortex-A5), increasing performance for large workloads such as web browsing.

In a 28nm process, the Cortex-A7 can run at 1.2-1.6GHz, has an area of 0.45mm2 (with Floating-Point Unit, Neon and a 32KB L1 cache) and requires less than 100mW of total power in typical conditions. This lowest performance profile makes it an ideal standalone processor for a range of mobile devices, and means the Cortex-A7 can ultimately deliver similar performance to the Cortex-A9 processor at much higher levels of power efficiency.


  • Manual containing technical information.
  • Cortex-A7 Technical Reference Manual

    For system designers and software engineers, the Cortex-A7 manual provides information on implementing and programming Cortex-A7 based devices.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the Guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio

    Development Tools

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A7 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-A7 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A7 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Mali GPUs

Mali Display Processors

Mali-V500 Video Processor

CoreLink Network Interconnect Family

CoreLink System Controllers

Interrupt Controllers

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

 

Community Blogs

Community Forums

Suggested answer 'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'
  • AXI
  • DesignStart
  • Support
  • Block
0 votes 587 views 3 replies Latest 14 hours ago by BBtheEE Answer this
Answered Looking for an eval board with octa core Armv8 CPU
  • AArch64
0 votes 350 views 9 replies Latest 15 hours ago by Dzik Answer this
Suggested answer setting brakpoint from code 0 votes 76 views 2 replies Latest 18 hours ago by Joseph Yiu Answer this
Answered aarch64 Exception Level Sw itch from EL1 to EL0 0 votes 140 views 7 replies Latest yesterday by michaelyuanfeng Answer this
Not answered reference source code to verify the Cortex-R52
  • cortex-r52
  • Evaluation Boards
0 votes 43 views 0 replies Started yesterday by Jorney Answer this
Answered Exclusive Access Restriction Clarification
  • AMBA
0 votes 1508 views 4 replies Latest yesterday by Taniya Garg Answer this
Suggested answer 'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L' Latest 14 hours ago by BBtheEE 3 replies 587 views
Answered Looking for an eval board with octa core Armv8 CPU Latest 15 hours ago by Dzik 9 replies 350 views
Suggested answer setting brakpoint from code Latest 18 hours ago by Joseph Yiu 2 replies 76 views
Answered aarch64 Exception Level Sw itch from EL1 to EL0 Latest yesterday by michaelyuanfeng 7 replies 140 views
Not answered reference source code to verify the Cortex-R52 Started yesterday by Jorney 0 replies 43 views
Answered Exclusive Access Restriction Clarification Latest yesterday by Taniya Garg 4 replies 1508 views