Cortex-A7 Technical Reference ManualThe main resource for hardware and software engineers implementing the Cortex-A7 processor in system designs.
Technical Reference Manual
Cortex-A Series Programmer's Guide for ARMv7-A
Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for ARMv7-A.Get the Guide
Development Tools for Cortex-A
ARM and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.Development Tools
|Multicore||1-4 cores. Symmetric Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 technology|
|Memory Management||ARMv7 Memory Management Unit (MMU)|
|Debug and Trace||CoreSight™ SoC-400|
In-order 8 stage pipeline
Improved dual issue, branch prediction and memory system performance. It features 64-bit load-store path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry).
Integrated, Configurable Size Level 2 Cache Controller
Provides low-latency and high-bandwidth access to up to 1MB of cached memory in high-frequency designs, or designs needing to reduce the power consumption associated with off-chip memory access. The L2 cache is optional on Cortex-A7.
Support ARMv7-A extensions
Hardware Virtualization and Large Physical Address Extensions (LPAE) enables the processor to access up to 1TB of memory.
First LITTLE processor architecturally compatible with compatible with Cortex-A15 and Cortex-A17 for various big.LITTLE processor combinations.
Cortex-A7 Power Efficiency Relative to Cortex-A9
The Cortex-A7 processor builds on the energy-efficient 8-stage pipeline of the Cortex-A5 processor. It also benefits from an integrated L2 cache designed for low-power, with lower transaction latencies and improved OS support for cache maintenance. On top of this there is improved branch prediction and an improved memory system performance, with 64-bit load-store path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry, up from 128 entry for Cortex-A9 and Cortex-A5), increasing performance for large workloads such as web browsing.
In a 28nm process, the Cortex-A7 can run at 1.2-1.6GHz, has an area of 0.45mm2 (with Floating-Point Unit, NEON and a 32KB L1 cache) and requires less than 100mW of total power in typical conditions. This lowest performance profile makes it an ideal standalone processor for a range of mobile devices, and means the Cortex-A7 can ultimately deliver similar performance to the Cortex-A9 processor at much higher levels of power efficiency.