Cortex-A72 Overview

The Cortex-A72 processor is an efficient high-performance processor that implements the ARMv8-A architecture, which can be paired with the Cortex-A53 processor in a big.LITTLE configuration for mobile applications. The Cortex-A72 processor cluster has one to four cores, each with their L1 instruction and data caches, together with a single shared L2 unified cache.

  • Cortex-A72 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource. Technical Reference Manual
  • Cortex-A Series Programmer's Guide for ARMv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for ARMv8-A.

    Programmer's Guide for ARMv8-A
  • Cortex-A72 Software Optimization Guide

    For software engineers and programmers, the software optimization guide examines the performance characteristics of instructions in detail.

    Software Optimization Guide
  • Development Tools for Cortex-A

    ARM and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools
  • Porting to ARM 64-bit

    If you are migrating from an ARMv7 architecture based design to the ARMv8 64-bit A64 instruction set, we provide a porting guide to help you.

    Porting to ARM 64-bit
  • Cortex-A Safety Documents Package

    For customers who needs to safety certify their end products, ARM provides a Safety Documentation Package for silicon developers and safety certified toolchain to accelerate the time to market.


Architecture ARMv8-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 5 CHI or AMBA 4 ACE technology
ISA Support
  • AArch32 for full backward compatibility with ARMv7
  • AArch64 for 64-bit support and new architectural features
  • TrustZone® security technology
  • NEON advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 floating point
  • Hardware virtualization support
Debug & Trace CoreSight™ DK-A72

Key Features

Triple-Issue Out-of-Order Pipeline

Dispatch and computational bandwidth improvements over Cortex-A57 have maximize the effectiveness of the triple-issue out-of-order pipeline to remove code dependencies for achieving high peak and sustained instruction throughputs at frequencies above 3GHz in 16FF+ process technology.

Advanced Branch Predictor

A sophisticated new algorithm drastically improves prediction accuracy which reduces wasted energy consumption from executing down a wrong code path.

Microarchitecture Efficiency

Every aspect of the Cortex-A57 microarchitecture was optimized to usher in a new level of Cortex-A energy efficiency with dramatic improvements in all aspects of PPA metrics (performance, power, and area).

Infrastructure Features

Support for networking and storage application with full ECC cache and 44-bit addressing up to 16TB.
Increased in sustained performance in smartphone power budget

Increased in sustained performance in smartphone power budget

Cortex-A72 Characteristics

The Cortex-A72 delivers 3.5x the sustained performance in the smartphone power envelope over 2014 28nm Cortex-A15 processor designs. The processor features several major micro-architectural improvements which build on the current generation of ARMv8-A cores. The enhancements in floating point, integer and memory performance improve the execution of every major class of workload. 

The processor is optimized for the 16nm FinFET process technology, enabling the Cortex-A72 to clock up to 2.5GHz in the mobile power envelope and leading to even higher total delivered performance.

On top of these key performance improvements, the Cortex-A72 CPU also benefits from significantly lower power consumption. This improved efficiency combined with the 16nm FinFET process technology enables the Cortex-A72 processor to achieve a 75% power reduction in representative premium mobile workloads.