Cortex-A72

The Cortex-A72 processor is an efficient high-performance processor that implements the Armv8-A architecture.

Information on arm Cortex-A72.

Getting Started

The Cortex-A72 processor can be paired with the Cortex-A53 processor in a big.LITTLE configuration for mobile applications. The Cortex-A72 processor cluster has one to four cores, each with their L1 instruction and data caches, together with a single shared L2 unified cache.

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Specifications

Architecture  Armv8-A
 Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 5 CHI or AMBA 4 ACE technology
 ISA Support
  • AArch32 for full backward compatibility with Armv7
  • AArch64 for 64-bit support and new architectural features
  • TrustZone security technology
  • Neon advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 floating point
  • Hardware virtualization support
 Debug & Trace

  • A guide on software optimization.
  • Cortex-A72 Software Optimization Guide

    For software engineers and programmers, the software optimization guide examines the performance characteristics of instructions in detail.

    Get the guide
  • Manual containing technical information.
  • Cortex-A72 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
  • Architecture A 62 guide
  • Porting to Arm 64-bit

    If you are migrating from an Armv7 architecture based design to the Armv8 64-bit A64 instruction set, we provide a porting guide to help you.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the guide
  • A manual that contains information on safety.
  • Cortex-A Safety Documents Package

    For customers who needs to safety certify their end products, Arm provides a Safety Documentation Package for silicon developers and safety certified toolchain to accelerate the time to market.

Get Support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A72 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-A72 processor can be incorporated into a SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A72 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Arm Mali-T860 and Mali-T880 (GPU)

Mali-DP550 (Display processor)

Mali-V550 (Video Processor)

CoreLink Cache Coherent Interconnect Family

CoreLink System Controllers

CoreLink DMC-500 and CoreLink DMC-520

CoreSight SoC-400

Arm POP (Physical IP)

Arm DS-5 Development Studio

Fixed Virtual Platforms

Arm Versatile Express

Arm Compiler 6

Arm Fast Models

Community Blogs


Community Forums

Not answered MPU and TrustZone 0 votes 14 views 0 replies Started 7 hours ago by Talk2Joseph Answer this
Suggested answer Cortex A15 SCU
  • Cortex-A15
  • Cortex-A
0 votes 265 views 1 replies Latest 8 hours ago by Christopher Tory Answer this
Suggested answer WT it non cache able memory when it broadcast at transaction
  • Cortex-A53
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0 votes 163 views 1 replies Latest 8 hours ago by Christopher Tory Answer this
Not answered Understanding XDMAC on Cortex-M7
  • cortex-m7
  • Cortex-M
0 votes 16 views 0 replies Started 8 hours ago by Paul Braman Answer this
Not answered How can I debug two A53 cores in DS-5 tool 0 votes 18 views 0 replies Started 18 hours ago by DriverLike Answer this
Suggested answer reference source code to verify the Cortex-R52
  • cortex-r52
  • Evaluation Boards
0 votes 89 views 1 replies Latest 19 hours ago by Jorney Answer this
Not answered MPU and TrustZone Started 7 hours ago by Talk2Joseph 0 replies 14 views
Suggested answer Cortex A15 SCU Latest 8 hours ago by Christopher Tory 1 replies 265 views
Suggested answer WT it non cache able memory when it broadcast at transaction Latest 8 hours ago by Christopher Tory 1 replies 163 views
Not answered Understanding XDMAC on Cortex-M7 Started 8 hours ago by Paul Braman 0 replies 16 views
Not answered How can I debug two A53 cores in DS-5 tool Started 18 hours ago by DriverLike 0 replies 18 views
Suggested answer reference source code to verify the Cortex-R52 Latest 19 hours ago by Jorney 1 replies 89 views