Cortex-A73

The Cortex-A73 processor is the most-efficient high-performance processor that implements the Armv8-A architecture.

Information on Cortex-A73.

Getting Started

The Cortex-A73 processor can be paired with the Cortex-A53 or Cortex-A35 processor in a big.LITTLE configuration for mobile applications. The Cortex-A73 processor cluster has one to four cores, each with their L1 instruction and data caches, together with a single shared L2 unified cache.


Specifications

Architecture  Armv8-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 ACE technology
ISA Support
  • AArch32 for full backward compatibility with Armv7
  • AArch64 for 64-bit support and new architectural features
  • TrustZone security technology
  • NEON advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 floating point
  • Hardware virtualization support
Debug & Trace
  • A guide on software optimization.
  • Cortex-A73 Software Optimization Guide

    For software engineers and programmers, the software optimization guide examines the performance characteristics of instructions in detail.

    Coming Soon

  • Manual containing technical information.
  • Cortex-A73 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
  • Architecture A 62 guide
  • Porting to Arm 64-bit

    If you are migrating from an Armv7 architecture based design to the Armv8 64-bit A64 instruction set, we provide a porting guide to help you.


    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Learn more
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the guide

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A73 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses   Arm Design Reviews  Open a support case

Related IP

The Cortex-A73 processor can be incorporated into a SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A73 processor is fully supported by Arm development tools. Related IP includes:

Graphic IP
Other IP
Tools

Mali-G71 GPU

Mali-DP550 display processor

Mali-V550 video processor

CoreLink CCI-550

CoreLink Interrupt Controllers

CoreLink System Controllers

TrustZone System IP

CoreLink DMC-500 and CoreLink DMC-520

CoreSight SoC-400

Arm POP IP

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

Community Blogs

Community Forums

Answered Whether Armv7-A has a Write Buffer 0 votes 474 views 8 replies Latest 4 days ago by Yang Wang Answer this
Answered dsb and dmb 0 votes 1102 views 11 replies Latest 6 days ago by digital_kevin Answer this
Answered Armv7 Store Buffer 0 votes 332 views 6 replies Latest 7 days ago by Yang Wang Answer this
Answered Digital design flow (synthesis) 0 votes 579 views 5 replies Latest 7 days ago by Joseph Yiu Answer this
Answered A panic function to halt the processor in low-power sleep using WFI? 1 votes 295 views 5 replies Latest 8 days ago by 42Bastian Schick Answer this
Answered SAU, IDAU, MPC and PPC. What's the difference?
  • Musca-A
  • TrustZone for Armv8-M
  • TrustZone
  • Cortex-M33
2 votes 226 views 2 replies Latest 8 days ago by Afonso Santos Answer this
Answered Whether Armv7-A has a Write Buffer Latest 4 days ago by Yang Wang 8 replies 474 views
Answered dsb and dmb Latest 6 days ago by digital_kevin 11 replies 1102 views
Answered Armv7 Store Buffer Latest 7 days ago by Yang Wang 6 replies 332 views
Answered Digital design flow (synthesis) Latest 7 days ago by Joseph Yiu 5 replies 579 views
Answered A panic function to halt the processor in low-power sleep using WFI? Latest 8 days ago by 42Bastian Schick 5 replies 295 views
Answered SAU, IDAU, MPC and PPC. What's the difference? Latest 8 days ago by Afonso Santos 2 replies 226 views