Cortex-A75

The Arm Cortex-A75 processor is Arm's latest and highest-performance application CPU delivering ground-breaking performance and market-leading power efficiency across a wide range of applications. 

Information on Cortex-A75.

Getting Started

Performance from edge to cloud

The Arm Cortex-A75 CPU is built on DynamIQ technology, enabling new levels of scalability and responsiveness for your advanced use cases. 

The processor is broadly applicable from cloud to edge, providing improvements in performance, efficiency, and architecture over its predecessors, the Cortex-A72 and Cortex-A73 processors. With significantly improved integer performance, and substantial enhancements in floating point and memory workloads performance, the Cortex-A75 processor is the most powerful Cortex-A processor to date.

This additional compute capability, combined with improvements for machine learning and other advanced use cases, will enable demanding applications to run more smoothly and provide a new baseline for even more complex workloads to be developed.

Learn more about Arm DynamIQ technology.


Specifications

General Architecture Armv8-A (Harvard)
  Extensions Armv8.1 extensions,
Armv8.2 extensions,
Cryptography extensions,
RAS extensions,
Armv8.3 (LDAPR instructions only)
  ISA Support A64, A32, and T32 instruction sets 
Microarchitecture Pipeline Out-of-order
  Superscalar Yes
  Neon / Floating Point Unit  Included
  Cryptography Unit
Optional
  Max Number of CPUs in Cluster Four (4)
  Physical Addressing (PA) 44-bit
Memory System and External Interfaces L1 I-Cache / D-Cache 64KB
  L2 Cache 256KB to 512KB 
  L3 Cache Optional 512KB to 4MB
  ECC Support Yes 
  LPAE Yes 
  Bus Interfaces ACE or CHI 
  ACP Optional 
  Peripheral Port Optional 
Other Functional Safety Support Safety package
  Security TrustZone 
  Interrupts GIC Interface, GICv4 
  Generic Timer  Armv8-A
  PMU PMUv3 
  Debug Armv8-A (plus Armv8.2-A extensions) 
  CoreSight CoreSightv3 
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

  • Manual containing technical information.
  • The Cortex-A75 Technical Reference Manual

    For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
  • A guide on software optimization.
  • Cortex-A Series Programmer’s Guide to Armv8.2-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for
    Armv8.2-A.

    Coming Soon

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A75 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Answered MMU and Cache configuration 0 votes 470 views 12 replies Latest 11 hours ago by Vanhealsing Answer this
Suggested answer Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification 0 votes 89 views 1 replies Latest 11 hours ago by Colin Campbell Answer this
Suggested answer Looking for an eval board with octa core Armv8 CPU
  • AArch64
0 votes 151 views 1 replies Latest 17 hours ago by Martin Weidmann Answer this
Suggested answer Store data directly in RAM - ARM Cortex A53 1 votes 165 views 2 replies Latest 17 hours ago by Martin Weidmann Answer this
Suggested answer DBM bit in descriptor 0 votes 127 views 3 replies Latest 20 hours ago by 42Bastian Schick Answer this
Suggested answer How to load the program into the FPGA ROM block is connected to the I/Dcode Bus ? 0 votes 119 views 1 replies Latest yesterday by Joseph Yiu Answer this
Answered MMU and Cache configuration Latest 11 hours ago by Vanhealsing 12 replies 470 views
Suggested answer Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification Latest 11 hours ago by Colin Campbell 1 replies 89 views
Suggested answer Looking for an eval board with octa core Armv8 CPU Latest 17 hours ago by Martin Weidmann 1 replies 151 views
Suggested answer Store data directly in RAM - ARM Cortex A53 Latest 17 hours ago by Martin Weidmann 2 replies 165 views
Suggested answer DBM bit in descriptor Latest 20 hours ago by 42Bastian Schick 3 replies 127 views
Suggested answer How to load the program into the FPGA ROM block is connected to the I/Dcode Bus ? Latest yesterday by Joseph Yiu 1 replies 119 views