Cortex-A75

The Arm Cortex-A75 processor is Arm's latest and highest-performance application CPU delivering ground-breaking performance and market-leading power efficiency across a wide range of applications. 

Information on Cortex-A75.

Getting Started

Performance from edge to cloud

The Arm Cortex-A75 CPU is built on DynamIQ technology, enabling new levels of scalability and responsiveness for your advanced use cases. 

The processor is broadly applicable from cloud to edge, providing improvements in performance, efficiency, and architecture over its predecessors, the Cortex-A72 and Cortex-A73 processors. With significantly improved integer performance, and substantial enhancements in floating point and memory workloads performance, the Cortex-A75 processor is the most powerful Cortex-A processor to date.

This additional compute capability, combined with improvements for machine learning and other advanced use cases, will enable demanding applications to run more smoothly and provide a new baseline for even more complex workloads to be developed.

Learn more about Arm DynamIQ technology.


Specifications

General Architecture Armv8-A (Harvard)
  Extensions Armv8.1 extensions,
Armv8.2 extensions,
Cryptography extensions,
RAS extensions,
Armv8.3 (LDAPR instructions only)
  ISA Support A64, A32, and T32 instruction sets 
Microarchitecture Pipeline Out-of-order
  Superscalar Yes
  Neon / Floating Point Unit  Included
  Cryptography Unit
Optional
  Max Number of CPUs in Cluster Four (4)
  Physical Addressing (PA) 44-bit
Memory System and External Interfaces L1 I-Cache / D-Cache 64KB
  L2 Cache 256KB to 512KB 
  L3 Cache Optional 512KB to 4MB
  ECC Support Yes 
  LPAE Yes 
  Bus Interfaces ACE or CHI 
  ACP Optional 
  Peripheral Port Optional 
Other Functional Safety Support Safety package
  Security TrustZone 
  Interrupts GIC Interface, GICv4 
  Generic Timer  Armv8-A
  PMU PMUv3 
  Debug Armv8-A (plus Armv8.2-A extensions) 
  CoreSight CoreSightv3 
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

  • Manual containing technical information.
  • The Cortex-A75 Technical Reference Manual

    For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
  • A guide on software optimization.
  • Cortex-A Series Programmer’s Guide to Armv8.2-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for
    Armv8.2-A.

    Coming Soon

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A75 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Not answered MPU and TrustZone 0 votes 13 views 0 replies Started 7 hours ago by Talk2Joseph Answer this
Suggested answer Cortex A15 SCU
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0 votes 265 views 1 replies Latest 7 hours ago by Christopher Tory Answer this
Suggested answer WT it non cache able memory when it broadcast at transaction
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0 votes 161 views 1 replies Latest 7 hours ago by Christopher Tory Answer this
Not answered Understanding XDMAC on Cortex-M7
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0 votes 14 views 0 replies Started 8 hours ago by Paul Braman Answer this
Not answered How can I debug two A53 cores in DS-5 tool 0 votes 18 views 0 replies Started 17 hours ago by DriverLike Answer this
Suggested answer reference source code to verify the Cortex-R52
  • cortex-r52
  • Evaluation Boards
0 votes 89 views 1 replies Latest 18 hours ago by Jorney Answer this
Not answered MPU and TrustZone Started 7 hours ago by Talk2Joseph 0 replies 13 views
Suggested answer Cortex A15 SCU Latest 7 hours ago by Christopher Tory 1 replies 265 views
Suggested answer WT it non cache able memory when it broadcast at transaction Latest 7 hours ago by Christopher Tory 1 replies 161 views
Not answered Understanding XDMAC on Cortex-M7 Started 8 hours ago by Paul Braman 0 replies 14 views
Not answered How can I debug two A53 cores in DS-5 tool Started 17 hours ago by DriverLike 0 replies 18 views
Suggested answer reference source code to verify the Cortex-R52 Latest 18 hours ago by Jorney 1 replies 89 views