Cortex-A76

The Cortex-A76 CPU delivers laptop-class performance with smartphone efficiency, bringing the same experience to all classes of intelligent mobile compute devices.

Information on Cortex-A76.

Getting Started

The Arm Cortex-A76 CPU is the second generation premium core built on DynamIQ technology. Paired with a Cortex-A55 CPU in a scalable DynamIQ big.LITTLE configuration, the Cortex-A76 delivers laptop-class performance with mobile efficiency, bringing the mobile experience (fast responsiveness, always on, always connected) into all classes of intelligent mobile compute devices. With superior energy efficiency and far greater single-threaded performance, the Cortex-A76 CPU extends battery life and improves user experience for sustained high performance across even the most complex compute tasks.

Key benefits

  • Better experience, user responsiveness, new ML/AI applications and virtual experiences.
  • Brings the always-on functionality of mobile to large screen devices, extending battery life for longer experiences.
  • 4x performance for inference ML at the edge.

Key features compared to Cortex-A75

  • 40% better power efficiency.
  • 35% improved performance.

Specifications

Architecture Armv8-A (Harvard)  
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 (LDAPR instructions only)

ISA support
  • A64
  • A32 and T32 (at the EL0 only)
 
Microarchitecture Pipeline Out-of-order
  Superscalar Yes
  Neon / Floating Point Unit Included
  Cryptography Unit Optional
  Max number of CPUs in cluster Four (4)
  Physical addressing (PA) 40-bit
Memory system and external interfaces L1 I-Cache / D-Cache 64KB
  L2 Cache 256KB to 512KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes
  LPAE Yes
  Bus interfaces AMBA ACE or CHI
  ACP Optional
  Peripheral Port Optional
Other Functional Safety Support ASIL D systematic
  Security TrustZone
  Interrupts GIC interface, GICv4
  Generic timer Armv8-A
  PMU PMUv3
  Debug Armv8-A (plus Armv8.2-A extensions)
  CoreSight CoreSightv3
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

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  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A76 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Answered JTAG to TrustZone Cortex-M33
  • secure systems
  • Secure Microcontroller
  • Microcontroller (MCU)
  • JTAG
  • security
  • STM32
  • TrustZone
  • Cortex-M33
0 votes 339 views 2 replies Latest 4 days ago by Ronan Synnott Answer this
Answered Cortex-M0+ privileged/unprivileged extensions
  • Armv6-M
  • cortex-m0+
0 votes 278 views 2 replies Latest 14 days ago by Joseph Yiu Answer this
Answered Development platforms, compilers for TrustZone
  • Toolchain
  • mbed OS
  • Keil
  • CMSIS
0 votes 363 views 1 replies Latest 14 days ago by Joseph Yiu Answer this
Answered Cortex-M0 DesignStart R2 1 votes 5870 views 13 replies Latest 19 days ago by muscle Answer this
Answered Non-secure peripheral with a secure interrupt handler 0 votes 581 views 5 replies Latest 23 days ago by Joseph Yiu Answer this
Answered Whether Armv7-A has a Write Buffer 0 votes 762 views 8 replies Latest 29 days ago by Yang Wang Answer this
Answered JTAG to TrustZone Cortex-M33 Latest 4 days ago by Ronan Synnott 2 replies 339 views
Answered Cortex-M0+ privileged/unprivileged extensions Latest 14 days ago by Joseph Yiu 2 replies 278 views
Answered Development platforms, compilers for TrustZone Latest 14 days ago by Joseph Yiu 1 replies 363 views
Answered Cortex-M0 DesignStart R2 Latest 19 days ago by muscle 13 replies 5870 views
Answered Non-secure peripheral with a secure interrupt handler Latest 23 days ago by Joseph Yiu 5 replies 581 views
Answered Whether Armv7-A has a Write Buffer Latest 29 days ago by Yang Wang 8 replies 762 views