Cortex-A76AE

The Cortex-A76AE is based on the second generation DynamIQ CPU, Cortex-A76 and comes with Split-Lock capability which includes Dual Core Lock-Step (DCLS), an advanced feature for increased fault tolerance designs.

Cotex-A76AE Block Diagram

Getting Started

The Cortex-A76AE is the first of an all new Arm Cortex-A family of Automotive Enhanced (AE), high performance processors. It is designed for devices undertaking complex and demanding safety critical tasks. The Cortex-A76AE is based on the second generation DynamIQ CPU, Cortex-A76 and comes with Dual Core Lock-Step (DCLS), an advanced feature for increased fault tolerance designs. 

The Cortex-A76AE is part of Arm's Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development. 

Key benefits

  • Split-Lock capability which offers the flexibility to operate in two modes; split mode for performance and lock mode for safety.
  • Fault-tolerant operation in lock mode with DCLS.
  • 4x performance for inference machine learning at the edge.

Key features compared to Cortex-A75

  • 40% better power efficiency per core.
  • 35% improved performance per core. 

Specifications

Architecture Armv8-A (Harvard)  
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 (LDAPR instructions only)

ISA support
  • A64
  • A32 and T32 (at the EL0 only)
 
Microarchitecture Pipeline Out-of-order
  Superscalar Yes
  Neon / Floating Point Unit Included
  Cryptography Unit Optional
  Max number of CPUs in cluster Four (4)
  Physical Addressing (PA) 40-bit
  Dual Core Lock-Step (DCLS) Yes (in safety-mode)
Memory system and external interfaces L1 I-Cache / D-Cache 64KB
  L2 Cache 256KB to 512KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes
  LPAE Yes
  Bus interfaces AMBA ACE or CHI
  ACP Optional
  Peripheral Port Optional
Other Functional Safety Support Supports ASIL D diagnostics
  Security TrustZone
  Interrupts GIC interface, GICv4
  Generic timer Armv8-A
  PMU PMUv3
  Debug Armv8-A (plus Armv8.2-A extensions)
  CoreSight CoreSightv3
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A76AE processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

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Answered AXI4 - read data interleaving
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Suggested answer M0+ Stack Pointer (PSP/MSP) Clarification
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Suggested answer ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence
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0 votes 39 views 0 replies Started yesterday by Nacho Renteria Answer this
Answered AXI4 - read data interleaving Latest 8 hours ago by hayk 9 replies 6542 views
Not answered How to start with Cortex-M1 Started 16 hours ago by Juanea7 0 replies 20 views
Suggested answer M0+ Stack Pointer (PSP/MSP) Clarification Latest 19 hours ago by Joseph Yiu 12 replies 407 views
Suggested answer ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence Latest 20 hours ago by 42Bastian Schick 2 replies 69 views
Not answered Non-secure EXC_RETURN value to Secure HardFault Handler Started yesterday by Rajiv 0 replies 8 views
Not answered M0 Synthesis Power Report Started yesterday by Nacho Renteria 0 replies 39 views