The Cortex-A76AE is the first of an all new Arm Cortex-A family of Automotive Enhanced (AE), high performance processors. It is designed for devices undertaking complex and demanding safety critical tasks. The Cortex-A76AE is based on the second generation DynamIQ CPU, Cortex-A76 and comes with Dual Core Lock-Step (DCLS), an advanced feature for increased fault tolerance designs.
The Cortex-A76AE is part of Arm's Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development.
- Split-Lock capability which offers the flexibility to operate in two modes; split mode for performance and lock mode for safety.
- Fault-tolerant operation in lock mode with DCLS.
- 4x performance for inference machine learning at the edge.
Key features compared to Cortex-A75
- 40% better power efficiency per core.
- 35% improved performance per core.
|NEON / Floating Point Unit||Included|
|Max number of CPUs in cluster||Four (4)|
|Physical Addressing (PA)||40-bit|
|Dual Core Lock-Step (DCLS)||Yes (in safety-mode)|
|Memory system and external interfaces||L1 I-Cache / D-Cache||64KB|
|L2 Cache||256KB to 512KB|
|L3 Cache||Optional, 512KB to 4MB|
|Bus interfaces||AMBA ACE or CHI|
|Other||Functional Safety Support||Supports ASIL D diagnostics|
|Interrupts||GIC interface, GICv4|
|Debug||Armv8-A (plus Armv8.2-A extensions)|
|Embedded Trace Macrocell||ETMv4.2 (instruction trace)|
Cortex-A Series Programmer's Guide for Armv8-A
Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.Get the guide
Development Tools for Cortex-A
Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.Development Tools
Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A76AE processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Arm Design Reviews Open a support case
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