Arm Cortex-M Series Processors

Optimized for cost and power sensitive MCU and mixed-signal devices for applications such as Internet of Things, connectivity, motor control, smart metering, human interface devices, automotive and industrial control systems, domestic household appliances, consumer products and medical instrumentation.

  • Cortex-M35P

    A tamper-resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.

  • Cortex-M33

    The Arm Cortex-M33 processor is the first feature rich implementation of the Armv8-M architecture.

  • Cortex-M23

    The Arm Cortex-M23 processor is the smallest and most energy efficient implementation of the Armv8-M architecture.

  • Cortex-M7

    The Arm Cortex-M7 processor is the highest performance member of the energy-efficient Cortex-M processor family.

  • Cortex-M4

    The Arm Cortex-M4 processor is Arm’s high performance embedded processor.

  • Cortex-M3

    The Arm Cortex-M3 processor is the industry-leading 32-bit processor for highly deterministic real-time applications.

  • Cortex-M0+

    The Arm Cortex-M0+ processor is the most energy efficient Arm processor available.

  • Cortex-M0

    The Arm Cortex-M0 processor is the smallest Arm processor available.

  • Arm DesignStart

    Design and produce an SoC with the widely-deployed Cortex-M0 and Cortex-M3 processors with no upfront license fee.

  • SC000 Processor

    The Arm SecurCore SC000 processor is designed specifically for the highest-volume smartcard and embedded security applications.

  • SC300 Processor

    The Arm SecurCore SC300 processor is designed specifically for high performance smartcard and embedded security applications.

Cortex-M Series Comparison

Cortex-M0

Cortex-M0+

Cortex-M3

Cortex-M4

Cortex-M7

Cortex-M23

Cortex-M33

Cortex-M35P

Instruction set architecture

Armv6-M
Thumb, Thumb-2

Armv6-M
Thumb, Thumb-2

Armv7-M
Thumb, Thumb-2

Armv7-M
Thumb, Thumb-2,
DSP, FP (SP)

Armv7-M
Thumb, Thumb-2,
DSP, FP (1. SP or 2. SP+DP)

Armv8-M baseline
Thumb, Thumb-2

Armv8-M mainline
Thumb, Thumb-2,
DSP, FP (SP)

Armv8-M mainline Thumb, Thumb-2,
DSP, FP (SP)

DMIPS/MHz range*

0.87-1.27

0.95-1.36

1.25-1.89

1.25-1.95

2.14-3.23

0.98-in progress

1.50-in progress

in progress

CoreMark®/MHz**

2.33

2.46

3.34

3.42

5.01

2.50

3.86

in progress

Memory Protection Unit (MPU)

No

Yes (option)

Yes (option)

Yes (option)

Yes (option)

Yes (option)(2 x)

Yes (option)(2 x)

Yes (option)(2 x)

Trace (ETM or MTB)

No

MTB (option)

ETMv3 (option)

ETMv3 (option)

ETMv4 (option)

MTB (option) or ETMv3

MTB (option) and/or ETMv4

MTB (option) and/or ETMv4

DSP

No

No

No

Yes

Yes

No

Yes (option)

Yes (option)

Floating point hardware

No

No

No

Yes (option SP)

Yes (option) 1. SP or 2. SP+DP

No

Yes (option)

Yes (option)

Systick Timer

Yes (option)

Yes (option)

Yes

Yes

Yes

Yes (2 x)

Yes (2 x)

Yes (2 x)

CMSIS Support

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Built-in caches

No

No

No

No

Yes (option 4-64kB I- and D-cache)

No

No

Yes (option)

Tightly-coupled memory

No

No

No

No

Yes (option 0-16MB I-TCM/D-TCM)

No

No

No

TrustZone for Armv8-M

No

No

No

No 

No 

Yes (option)

Yes (option) 

Yes (option)

Co-processor interface

No 

No 

No 

No 

No 

No 

Yes (option)

Yes (option)

*The lower result abides by all of the “ground rules” laid out in the Dhrystone documentation  while the upper bound additionally permits simultaneous (”multi-file”) compilation.
**Cortex-M23 and Cortex-M33 results are preliminary. The others are published on the EEMBC website.