Cortex-M0 Overview

The ARM Cortex-M0 processor is the smallest ARM processor available. The exceptionally small silicon area, low power and minimal code footprint of the processor enables developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices.

The ultra-low gate count of the Cortex-M0 processor also enables its deployment in analog and mixed signal devices. Available in a low-cost, easy-to-access package.

Try a Cortex-M0 for free

The Cortex-M0 is available in ARM’s DesignStart portal so designers can use a Cortex-M0 for free, and then once ready to commercialize their product, they can do this with a low-cost, simplified, fast-track license.

Start designing with Cortex-M0
  • Cortex-M0 Technical Reference Manual

    In-depth material for system designers, integrators and verification engineers. An important resource for software developers who want to make use of the Cortex-M0.

    Technical Reference Manual
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Get the White Paper
  • Embedded Development Tools for Cortex-M Series

    ARM and its ecosystem partners provide a wide range of tools for embedded software development on ARM Cortex-M processors.

    Software Tools for Cortex-M
  • CMSDK
  • Cortex-M System Design Kit (CMSDK)

    CMSDK is a comprehensive system solution designed to work seamlessly with Cortex-M processors out-of-the-box. 

    Learn more about CMSDK

Highlights

ISA Support Thumb® / Thumb-2 subset
Pipeline 3-stage
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Sleep Modes Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with ARM Power Management Kit
Bit Manipulation Bit banding region can be implemented with Cortex-M System Design Kit
Enhanced Instructions Hardware single-cycle (32x32) multiply option
Debug Optional JTAG or Serial-Wire Debug Ports. Up to 4 Breakpoints and 2 Watchpoints


Key Features

Exceptional code density

On average, the mix between 16bit and 32bit instructions yields a better code density when compared to 8bit and 16bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory.

Binary upward compatible with all other Cortex-M processors

The Cortex-M0 has mainly 16bit Thumb-2 instructions and few 32bit ones. These instructions are also present on all the other Cortex-M processors. Hence all code written  for the Cortex-M0 will run as is on the other processors.

Built-in low-power features

Sleep, deep sleep and state retention are three low power modes available to the user. 

Optional Debug Access Port and Serial Wire Debug

For devices where every pin counts the serial wire debug port uses only two pins.

Cortex-M0 Characteristics

Performance Efficiency: 2.33 CoreMarks/MHz* and 0.87 / 1.02 / 1.27 DMIPS/MHz**.

ARM Cortex-M0 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 25°C)
Dynamic Power 64.3µW/MHz 12.5µW/MHz 5.1µW/MHz
Floorplanned Area 0.109 mm2 0.030 mm2 0.007 mm2

* See: http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1509&suite=CORE

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone

*** Base usable configuration includes 1 IRQ + NMI, excludes debug