Cortex-M0

The Arm Cortex-M0 processor is the smallest Arm processor available. 

Information on Cortex-M0.

Getting Started

The exceptionally small silicon area, low power and minimal code footprint of the processor enables developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices.

The ultra-low gate count of the Cortex-M0 processor also enables its deployment in analog and mixed signal devices. Arm DesignStart provides free access to design and license the Cortex-M0, and free forum support to accelerate custom SoC development. It is the fastest, simplest, no-risk route to custom silicon success.

Download this whitepaper for tips and tools to creating an SoC proof-of-concept, free and fast!


Specifications

ISA Support Thumb/Thumb-2 subset
Pipeline

3-stages

Bit Manipulation
Bit banding region can be implemented with Cortex-M System Design Kit
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Enhanced Instructions
Hardware single-cycle (32x32) multiply option
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with Arm Power Management Kit
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.

Cortex-M0 Characteristics

Performance Efficiency 2.33 CoreMarks/MHz* and 0.89/1.02/1.27 DMIPS/MHz.

Arm Cortex-M0 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C) 
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 25°C)
Dynamic Power

66μW/MHz 

12.5μW/MHz 

5.3μW/MHz 

Floor planned Area

0.11 mm2

0.03 mm2

0.008 mm2

* See: http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1509&suite=CORE

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi- le”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

*** Configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug


  • Manual containing technical information.
  • Cortex-M0 Technical Reference Manual

    In-depth material for system designers, integrators and verification engineers. An important resource for software developers who want to make use of the Cortex-M0.

    Read here
  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more
  • A system design kit for apps.
  • Cortex-M System Design Kit (CMSDK)

    CMSDK is a comprehensive system solution designed to work seamlessly with Cortex-M processors out-of-the-box.

    Learn more

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M0 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Not answered MPU and TrustZone 0 votes 14 views 0 replies Started 7 hours ago by Talk2Joseph Answer this
Suggested answer Cortex A15 SCU
  • Cortex-A15
  • Cortex-A
0 votes 265 views 1 replies Latest 8 hours ago by Christopher Tory Answer this
Suggested answer WT it non cache able memory when it broadcast at transaction
  • Cortex-A53
  • Cortex-A
0 votes 162 views 1 replies Latest 8 hours ago by Christopher Tory Answer this
Not answered Understanding XDMAC on Cortex-M7
  • cortex-m7
  • Cortex-M
0 votes 14 views 0 replies Started 8 hours ago by Paul Braman Answer this
Not answered How can I debug two A53 cores in DS-5 tool 0 votes 18 views 0 replies Started 18 hours ago by DriverLike Answer this
Suggested answer reference source code to verify the Cortex-R52
  • cortex-r52
  • Evaluation Boards
0 votes 89 views 1 replies Latest 19 hours ago by Jorney Answer this
Not answered MPU and TrustZone Started 7 hours ago by Talk2Joseph 0 replies 14 views
Suggested answer Cortex A15 SCU Latest 8 hours ago by Christopher Tory 1 replies 265 views
Suggested answer WT it non cache able memory when it broadcast at transaction Latest 8 hours ago by Christopher Tory 1 replies 162 views
Not answered Understanding XDMAC on Cortex-M7 Started 8 hours ago by Paul Braman 0 replies 14 views
Not answered How can I debug two A53 cores in DS-5 tool Started 18 hours ago by DriverLike 0 replies 18 views
Suggested answer reference source code to verify the Cortex-R52 Latest 19 hours ago by Jorney 1 replies 89 views