Cortex-M0+ Overview

The ARM Cortex-M0+ processor is the most energy efficient ARM processor available. It builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance. Along with the Cortex-M0 processor, the exceptionally small silicon area, low power and minimal code footprint of these processors enable developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.

  • Cortex-M0+ Technical Reference Manual

    For system designers, integrators and testers, the Cortex-M0+ TRM provides low level microarchitectural detail of the Cortex-M0+ processor.

    Technical Reference Manual

Highlights

ISA Support Thumb® / Thumb-2 subset
Pipeline 2 stage
Memory Protection Optional 8 region MPU with sub regions and background region
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Sleep Modes Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with ARM Power Management Kit
Bit Manipulation Bit banding region can be implemented with Cortex-M System Design Kit
Enhanced Instructions Hardware single-cycle (32x32) multiply option
Debug Optional JTAG or Serial-Wire Debug Ports Up to 4 Breakpoints and 2 Watchpoints
Trace Optional Micro Trace Buffer

Key Features

Memory protection unit

Software reliability improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data

Binary upward compatible with all other Cortex-M processors

The Cortex-M0+ has mainly 16bit Thumb-2 instructions and few 32bit ones. These instructions are also present on all the other Cortex-M processors. Hence all code written  for the Cortex-M0+ will run as is on the other processors

Built-in low-power features

Sleep, deep sleep and state retention are three low power modes available to the user

Optional Debug Access Port and Serial Wire Debug

For devices where every pin counts the serial wire debug port uses only two pins

Optional Micro Trace Buffer

Trace all program flow via an in-memory trace buffer which can be read out via JTAG for later analysis

Characteristics

Performance Efficiency 2.46 CoreMarks/MHz* and 0.95/1.11/1.35 DMIPS/MHz**.

ARM Cortex-M0+ Implementation Data***
180ULL 
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP 
(9-track, typical 1.1v, 25°C)
Dynamic Power 47.4 µW/MHz 9.37 µW/MHz 3.8 µW/MHz
Floorplanned Area 0.098 mm2 0.028 mm2 0.0066 mm2

http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1526&suite=CORE

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone

*** Base usable configuration includes 1 IRQ + NMI, excludes debug