The Arm Cortex-M0+ processor is the most energy efficient Arm processor available.


The Cortex-M0+ processor builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance. Along with the Cortex-M0 processor, the exceptionally small silicon area, low power and minimal code footprint of these processors enable developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.

Block Diagram on Cortex-M0+.

Key benefits

  • Extremely low power. The most energy efficient of all Arm processors. The Cortex-M0+ achieves a power consumption below 4µW/MHz (40LP process, base configuration), while reaching a performance of 2.46 CoreMark/MHz.

  • Versatile. The Cortex-M0+ includes optional functionalities that allow designers to reach an optimal fit-for-purpose solution for a broad range of applications. These include the single-cycle I/O interface for faster control, the Micro Trace Buffer (MTB) for enhanced debug, and others which are common to all Cortex-M processors, such as the Memory Protection Unit (MPU) and the relocatable vectortable.

  • Fast time-to-market. The Cortex-M0+ processor is binary compatible to the Cortex-M0 and is upward binary compatible to all other Cortex-M processors making software re-use a real advantage. Developers also benefit from the Arm partnership’s extensive ecosystem of embedded tools, software, and knowledge base.


ISA Support Thumb/Thumb-2 subset.
Pipeline 2-stage.
Memory Protection
Optional 8 region MPU with sub regions and background region.
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts.
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit.
Bit Manipulation
Bit banding region can be implemented with Cortex-M System Design Kit.
Enhanced Instructions
Hardware single-cycle (32x32) multiply option.
Optional JTAG or Serial Wire Debug ports Up to 4 Breakpoints and 2 Watchpoints.
Optional Micro Trace Buffer.

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The Cortex-M0+ processor brings the highest energy-efficiency to cost-sensitive devices. It is suitable for a wide variety of applications.

MEMS sensors

Power management


Digital motor control


Low power MCUs


Health wearable monitors


Environmental monitors

Key Features

Memory protection unit

Software reliability improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data.

Binary upward compatible with all other Cortex-M processors

The Cortex-M0+ has mainly 16bit Thumb-2 instructions and few 32bit ones. These instructions are also present on all the other Cortex-M processors. Hence all code written  for the Cortex-M0+ will run as is on the other processors.

Built-in low-power features

Sleep, deep sleep and state retention are three low power modes available to the user.

Optional Debug Access Port and Serial Wire Debug

For devices where every pin counts the serial wire debug port uses only two pins.

Optional Micro Trace Buffer

Trace all program flow via an in-memory trace buffer which can be read out via JTAG for later analysis.


Performance Efficiency 2.46 CoreMarks/MHz* and 0.95/1.11/1.35 DMIPS/MHz**.

Arm Cortex-M0+ Implementation Data***
(7-track, typical 1.8v, 25°C)
(7-track, typical 1.2v, 25°C)
(9-track, typical 1.1v, 25°C)
Dynamic Power 47.4 µW/MHz 9.37 µW/MHz 3.8 µW/MHz
Floorplanned Area 0.098 mm2 0.028 mm2 0.0066 mm2

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.

*** Base usable configuration includes 1 IRQ + NMI, excludes debug.


Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M0+ processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses Arm Design Reviews

  • Manual containing technical information.
  • Cortex-M0+ Technical Reference Manual

    In-depth material for system designers, integrators and verification engineers. An important resource for software developers who want to make use of the Cortex-M0+.

    Read here
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  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more

  • Product due to be released to  market.
  • Arm Design Reviews

    Arm's on-site design review service gives licensees confidence that their Cortex-M0+ CPU is implemented efficiently, to provide maximum system performance, with lowest risk and fastest time-to-market.

    Learn more
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  • Questions? Request more information

    Learn more about Cortex-A75, Arm’s  most energy efficient Arm processor available. Contact us to speak with our technical team.

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