The Cortex-M0+ processor builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance. Along with the Cortex-M0 processor, the exceptionally small silicon area, low power and minimal code footprint of these processors enable developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.
|ISA Support||Thumb/Thumb-2 subset.|
||Optional 8 region MPU with sub regions and background region.|
|Interrupts||Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts.|
||Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit.
||Bit banding region can be implemented with Cortex-M System Design Kit.|
||Hardware single-cycle (32x32) multiply option.|
||Optional JTAG or Serial Wire Debug ports Up to 4 Breakpoints and 2 Watchpoints.|
||Optional Micro Trace Buffer.|
Performance Efficiency 2.46 CoreMarks/MHz* and 0.95/1.11/1.35 DMIPS/MHz**.
|Arm Cortex-M0+ Implementation Data***|
(7-track, typical 1.8v, 25°C)
(7-track, typical 1.2v, 25°C)
(9-track, typical 1.1v, 25°C)
|Dynamic Power||47.4 µW/MHz||9.37 µW/MHz||3.8 µW/MHz|
|Floorplan Area||0.098 mm2||0.028 mm2||0.0066 mm2|
** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.
*** Base usable configuration includes 1 IRQ + NMI, excludes debug.
Cortex-M0+ Technical Reference Manual
In-depth material for system designers, integrators and verification engineers. An important resource for software developers who want to make use of the Cortex-M0+.Read here
White Paper: Cortex-M for beginners
This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.Read here
Embedded Development Tools for Cortex-M Series
Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.Learn more
Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M0+ processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Arm Design Reviews Open a support case
The Cortex-M0+ processor can be incorporated into a SoC using a broad range of Arm technology including System IP, and Physical IP. It is fully supported by Arm development tools. Related IP includes:
|Not answered||MPU and TrustZone||0 votes||15 views||0 replies||Started 8 hours ago by Talk2Joseph||Answer this|
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|Suggested answer||reference source code to verify the Cortex-R52||0 votes||91 views||1 replies||Latest 19 hours ago by Jorney||Answer this|
|Not answered||MPU and TrustZone Started 8 hours ago by Talk2Joseph||0 replies 15 views|
|Suggested answer||Cortex A15 SCU Latest 9 hours ago by Christopher Tory||1 replies 267 views|
|Suggested answer||WT it non cache able memory when it broadcast at transaction Latest 9 hours ago by Christopher Tory||1 replies 165 views|
|Not answered||Understanding XDMAC on Cortex-M7 Started 9 hours ago by Paul Braman||0 replies 17 views|
|Not answered||How can I debug two A53 cores in DS-5 tool Started 19 hours ago by DriverLike||0 replies 19 views|
|Suggested answer||reference source code to verify the Cortex-R52 Latest 19 hours ago by Jorney||1 replies 91 views|