Cortex-M0+

The Arm Cortex-M0+ processor is the most energy-efficient Arm processor available.

Block Diagram on Cortex-M0+.

Getting Started

The Cortex-M0+ processor builds on the very successful Cortex-M0 processor, retaining full instruction set and tool compatibility, while further reducing energy consumption and increasing performance. Along with the Cortex-M0 processor, the exceptionally small silicon area, low power and minimal code footprint of these processors enable developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The Cortex-M0+ processor comes with a wide selection of options to provide flexible development.

Specifications

ISA Support Thumb/Thumb-2 subset.
Pipeline 2-stage.
Memory Protection
Optional 8 region MPU with sub regions and background region.
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts.
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit.
Bit Manipulation
Bit banding region can be implemented with Cortex-M System Design Kit.
Enhanced Instructions
Hardware single-cycle (32x32) multiply option.
Debug
Optional JTAG or Serial Wire Debug ports Up to 4 Breakpoints and 2 Watchpoints.
Trace
Optional Micro Trace Buffer.

Characteristics

Performance Efficiency 2.46 CoreMarks/MHz* and 0.95/1.11/1.35 DMIPS/MHz**.

Arm Cortex-M0+ Implementation Data***
180ULL 
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP 
(9-track, typical 1.1v, 25°C)
Dynamic Power 47.4 µW/MHz 9.37 µW/MHz 3.8 µW/MHz
Floorplan Area 0.098 mm2 0.028 mm2 0.0066 mm2

http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1526&suite=CORE

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.

*** Base usable configuration includes 1 IRQ + NMI, excludes debug.



  • Manual containing technical information.
  • Cortex-M0+ Technical Reference Manual

    In-depth material for system designers, integrators and verification engineers. An important resource for software developers who want to make use of the Cortex-M0+.

    Read here
  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M0+ processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

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Suggested answer DWT 0 votes 139 views 1 replies Latest 7 days ago by Joseph Yiu Answer this
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest 3 days ago by a.surati 1 replies 100 views
Answered Whether Armv7-A has a Write Buffer Latest 4 days ago by Yang Wang 8 replies 474 views
Suggested answer Why AXI4 changed the definition of AxCACHE? Latest 5 days ago by Colin Campbell 1 replies 145 views
Suggested answer AXI read response in error case Latest 6 days ago by Colin Campbell 1 replies 154 views
Answered dsb and dmb Latest 6 days ago by digital_kevin 11 replies 1103 views
Suggested answer DWT Latest 7 days ago by Joseph Yiu 1 replies 139 views