Cortex-M1

The first Arm processor designed specifically for implementation in FPGAs. 

Getting Started

The Cortex-M1 processor targets FPGA devices and includes support for leading FPGA synthesis tools allowing the designer to choose the optimal implementation for each project. The Cortex-M1 processor enables OEMs to achieve significant cost savings through rationalization of software and tools investments across multiple projects spanning FPGA, ASIC and ASSP, plus greater vendor independence through use of an industry-standard processor.

Key features

  • Three-stage, 32-bit RISC processor
  • Thumb-2 instruction set
  • Integrated nested vectored interrupt controller
  • Fast or small multiplier configuration options

DesignStart FPGA

Get instant access to Cortex-M1 on Xilinx FPGA.


Specifications

Architecture Armv6-M
ISA Thumb and Thumb-2 (except CBZ, CBNZ, IT, BL, DMB, DSB, ISB, MRS, MSR)
Pipeline Three-stage
SysTick Timer Optional
Bit Manipulation Optional bit-banding
Interrupts 1 – 32 interrupts (configurable)
Interrupt Priority Levels 4 priority levels per interrupt
Instruction and Data Tightly Coupled Memories 0K - 1024K (configurable)
Debug Full or reduced debug (full - 4 breakpoint comparators, 2 watchpoint comparators)
  • Manual containing technical information.
  • Cortex-M1 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M1 processor.

    Read here
  • Manual containing technical information.
  • Cortex-M1 FPGA Development Kit Cortex-M1 User Guide

    For FPGA system designers and programmers who want to incorporate and program the Cortex-M1 processor in their own SoC design using an Altera FPGA and Altera System-On-a-Programmable-Chip (SOPC) Builder. 

    Read here
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more
  • Manual containing technical information.
  • Cortex-M Resources

    Further resources for Cortex-M developers. 

    Read here

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M1 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Forums

Answered AXI4 - read data interleaving
  • AMBA
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  • AXI4
  • interleaving
0 votes 6542 views 9 replies Latest 8 hours ago by hayk Answer this
Not answered How to start with Cortex-M1
  • cortex-m1
0 votes 20 views 0 replies Started 16 hours ago by Juanea7 Answer this
Suggested answer M0+ Stack Pointer (PSP/MSP) Clarification
  • Cortex-M0
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  • cortex-m0+
0 votes 407 views 12 replies Latest 19 hours ago by Joseph Yiu Answer this
Suggested answer ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence
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  • Cache coherency
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  • Cortex-R5
0 votes 69 views 2 replies Latest 20 hours ago by 42Bastian Schick Answer this
Not answered Non-secure EXC_RETURN value to Secure HardFault Handler 0 votes 8 views 0 replies Started yesterday by Rajiv Answer this
Not answered M0 Synthesis Power Report
  • Cortex-M0
  • DesignStart
0 votes 39 views 0 replies Started yesterday by Nacho Renteria Answer this
Answered AXI4 - read data interleaving Latest 8 hours ago by hayk 9 replies 6542 views
Not answered How to start with Cortex-M1 Started 16 hours ago by Juanea7 0 replies 20 views
Suggested answer M0+ Stack Pointer (PSP/MSP) Clarification Latest 19 hours ago by Joseph Yiu 12 replies 407 views
Suggested answer ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence Latest 20 hours ago by 42Bastian Schick 2 replies 69 views
Not answered Non-secure EXC_RETURN value to Secure HardFault Handler Started yesterday by Rajiv 0 replies 8 views
Not answered M0 Synthesis Power Report Started yesterday by Nacho Renteria 0 replies 39 views