Cortex-M1

The first Arm processor designed specifically for implementation in FPGAs. 

Cortex-M1

Overview

The Cortex-M1 processor targets FPGA devices and includes support for leading FPGA synthesis tools allowing the designer to choose the optimal implementation for each project. The Cortex-M1 processor enables OEMs to achieve significant cost savings through rationalization of software and tools investments across multiple projects spanning FPGA, ASIC and ASSP, plus greater vendor independence through use of an industry-standard processor.

Key features

  • Three-stage, 32-bit RISC processor

  • Thumb-2 instruction set

  • Integrated nested vectored interrupt controller

  • Fast or small multiplier configuration options

Highlights

Architecture

Armv6-M

ISA

Thumb and Thumb-2 (except CBZ, CBNZ, IT, BL, DMB, DSB, ISB, MRS, MSR)

Pipeline

Three-stage

SysTick Timer

Optional

Bit Manipulation

Optional bit-banding

Interrupts

1 – 32 interrupts (configurable)

Interrupt Priority Levels

4 priority levels per interrupt

Instruction and Data Tightly Coupled Memories

0K - 1024K (configurable)

Debug

Full or reduced debug (full - 4 breakpoint comparators, 2 watchpoint comparators)

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Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M1 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

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