The Cortex-M23 processor is a very compact, two-stage pipelined processor that supports the Armv8-M baseline instruction set. The Cortex-M23 with TrustZone is the ideal processor for the most constrained embedded applications where security is a key requirement.
TrustZone for Armv8-M provides hardware-enforced isolation between the trusted and the untrusted resources on the Cortex-M23 device, while maintaining the efficient exception handling and determinism that have been the hallmark of all Cortex-M processors.
Everything you need to know about TrustZone for Armv8-M is here.
|Architecture||Armv8-M Baseline (Von Neumann)|
|ISA Support||Thumb/Thumb-2 subset|
|TrustZone||Optional TrustZone for Armv8-M|
|Memory Protection||Optional Memory Protection Unit (MPU) with up to 16 regions per security state|
|Interrupts||Non-maskable Interrupt (NMI) and up to 240 physical interrupts with 4 priority levels|
|Wake-up Interrupt Controller||Optional for waking up the processor from state retention power gating or when all clocks are stopped|
|Sleep Modes||Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
|Enhanced Instructions||Hardware single-cycle (32x32) multiply and fast (32/32) divide option|
|Debug||Optional JTAG or Serial Wire Debug ports, up to 4 Breakpoints and 4 Watchpoints|
|Trace||Optional Micro Trace Buffer (MTB) or Embedded Trace Macrocell (ETM)|
Performance efficiency 2.50 CoreMark/MHz* and 0.98 DMIPS/Mhz**.
|Arm Cortex-M23 implementation data at 40LP (9-track, typical 1.1v, 25°C)
||Please contact Arm
||Please contact Arm|
||Please contact Arm||Please contact Arm|
* Preliminary data.
** Preliminary data, abides by all of the ground rules laid out in the Dhrystone documentation.
Cortex-M23 Technical Reference Manual
For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M23 processor.Read here
White Paper: Armv8-M Architecture
Download this White Paper to get a technical overview of the Armv8-M architecture and an introduction to TrustZone security technology.Read here
White Paper: Cortex-M for beginners
This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.Read here
Embedded Development Tools for Cortex-M Series
Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.Learn more
Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M23 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Arm Design Reviews Open a support case
The Cortex-M23 processor can be incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:
|Not answered||MPU and TrustZone||0 votes||24 views||0 replies||Started 15 hours ago by Talk2Joseph||Answer this|
|Suggested answer||Cortex A15 SCU||0 votes||275 views||1 replies||Latest 16 hours ago by Christopher Tory||Answer this|
|Suggested answer||WT it non cache able memory when it broadcast at transaction||0 votes||174 views||1 replies||Latest 16 hours ago by Christopher Tory||Answer this|
|Not answered||Understanding XDMAC on Cortex-M7||0 votes||23 views||0 replies||Started 16 hours ago by Paul Braman||Answer this|
|Not answered||How can I debug two A53 cores in DS-5 tool||0 votes||28 views||0 replies||Started yesterday by DriverLike||Answer this|
|Suggested answer||reference source code to verify the Cortex-R52||0 votes||105 views||1 replies||Latest yesterday by Jorney||Answer this|
|Not answered||MPU and TrustZone Started 15 hours ago by Talk2Joseph||0 replies 24 views|
|Suggested answer||Cortex A15 SCU Latest 16 hours ago by Christopher Tory||1 replies 275 views|
|Suggested answer||WT it non cache able memory when it broadcast at transaction Latest 16 hours ago by Christopher Tory||1 replies 174 views|
|Not answered||Understanding XDMAC on Cortex-M7 Started 16 hours ago by Paul Braman||0 replies 23 views|
|Not answered||How can I debug two A53 cores in DS-5 tool Started yesterday by DriverLike||0 replies 28 views|
|Suggested answer||reference source code to verify the Cortex-R52 Latest yesterday by Jorney||1 replies 105 views|