Cortex-M23

The Cortex-M23 processor is the smallest and most energy-efficient implementation of the Armv8-M architecture.

Block Diagram on Cortex-M23.

Getting Started

The Cortex-M23 processor is a very compact, two-stage pipelined processor that supports the Armv8-M baseline instruction set. The Cortex-M23 with TrustZone is the ideal processor for the most constrained embedded applications where security is a key requirement. 

TrustZone for Armv8-M provides hardware-enforced isolation between the trusted and the untrusted resources on the Cortex-M23 device, while maintaining the efficient exception handling and determinism that have been the hallmark of all Cortex-M processors. 

Everything you need to know about TrustZone for Armv8-M is here.


Specifications

Architecture Armv8-M Baseline (Von Neumann)
ISA Support Thumb/Thumb-2 subset
Pipeline Two-stage
TrustZone Optional TrustZone for Armv8-M
Memory Protection Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-maskable Interrupt (NMI) and up to 240 physical interrupts with 4 priority levels
Wake-up Interrupt Controller Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Enhanced Instructions Hardware single-cycle (32x32) multiply and fast (32/32) divide option
Debug Optional JTAG or Serial Wire Debug ports, up to 4 Breakpoints and 4 Watchpoints
Trace Optional Micro Trace Buffer (MTB) or Embedded Trace Macrocell (ETM)

Characteristics

Performance efficiency 2.50 CoreMark/MHz* and 0.98 DMIPS/Mhz**.

Arm Cortex-M23 implementation data at 40LP (9-track, typical 1.1v, 25°C)
  No TrustZone
With TrustZone
Dynamic Power
Please contact Arm
Please contact Arm
Floorplan Area
Please contact Arm Please contact Arm

* Preliminary data.
** Preliminary data, abides by all of the ground rules laid out in the Dhrystone documentation.

  • Manual containing technical information.
  • Cortex-M23 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M23 processor.

    Read here
  • A program that is running on a desktop.
  • White Paper: Armv8-M Architecture

    Download this White Paper to get a technical overview of the Armv8-M architecture and an introduction to TrustZone security technology.

    Read here
  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M23 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-M23 processor can be incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:

Compatible IP
Tools
Software

AMBA System Controllers

CoreLink SIE-200

TrustZone CryptoCell-312

Arm CoreLink CG092

AHB flash cache

Physical IP

DS-5 Development Studio

Arm Keil MDK software development tool

Arm Compiler

Cortex-M Prototyping System

Fast Models

TrustZone for Armv8-M

Cortex Microcontroller Software Interface Standard

Arm Mbed Pelion Device Platform

Community Blogs

Community Forums

Suggested answer M0+ Stack Pointer (PSP/MSP) Clarification
  • Cortex-M0
  • R13 (SP Stack Pointer)
  • cortex-m0+
0 votes 540 views 14 replies Latest 8 hours ago by Sean Dunlevy Answer this
Answered Using uVision Eval version with Xilinx DesignStart examples 0 votes 53 views 1 replies Latest 16 hours ago by Sean Houlihane Answer this
Answered ARMv8-A: Virtual to physical translation sometime "fails"
  • Armv8-A
0 votes 53 views 1 replies Latest 19 hours ago by 42Bastian Schick Answer this
Suggested answer Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped
  • Cortex-A9
  • CoreLink L2C-310 Level 2 Cache Controller
0 votes 433 views 6 replies Latest 22 hours ago by teamrtos Answer this
Not answered Why is PC-relative addressing deprecated for STR and VSTR in ARMv7-M4? 0 votes 36 views 0 replies Started yesterday by Dan Lewis Answer this
Suggested answer TSMC CE018FG Library - Synthesis
  • Cortex-M0
  • Standard Cell Libraries
  • DesignStart
0 votes 74 views 1 replies Latest yesterday by Joseph Yiu Answer this
Suggested answer M0+ Stack Pointer (PSP/MSP) Clarification Latest 8 hours ago by Sean Dunlevy 14 replies 540 views
Answered Using uVision Eval version with Xilinx DesignStart examples Latest 16 hours ago by Sean Houlihane 1 replies 53 views
Answered ARMv8-A: Virtual to physical translation sometime "fails" Latest 19 hours ago by 42Bastian Schick 1 replies 53 views
Suggested answer Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped Latest 22 hours ago by teamrtos 6 replies 433 views
Not answered Why is PC-relative addressing deprecated for STR and VSTR in ARMv7-M4? Started yesterday by Dan Lewis 0 replies 36 views
Suggested answer TSMC CE018FG Library - Synthesis Latest yesterday by Joseph Yiu 1 replies 74 views