Cortex-M3

The Arm Cortex-M3 processor is the industry-leading 32-bit processor for highly deterministic real-time applications. 

Block Diagram on Cortex-M3.

Getting Started

The Cortex-M3 processor is specifically developed to enable partners to develop high-performance low-cost platforms for a broad range of devices including microcontrollers, automotive body systems, industrial control systems and wireless networking and sensors.

DesignStart helps companies design innovative custom chips or FPGA designs, with the lowest risk possible. You can access the Cortex-M3 via DesignStart for no upfront fee. 

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Specifications

Architecture Armv7-M Harvard
ISA Support Thumb/Thumb-2
Pipeline three-stage
Memory Protection
Optional 8 region MPU with sub regions and background region
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt Controller
Up to 240 Wake-up Interrupts
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit
Bit Manipulation Integrated Instructions & Bit Banding
Enhanced Instructions Hardware Divide (2-12 Cycles), Single-Cycle (32x32) Multiply, Saturated Math Support
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.

Trace

Optional Instruction (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)

Fast access to Cortex-M3

Access Cortex-M3 for $0 upfront for custom chips or FPGA designs with Arm DesignStart.

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Characteristics

Performance Efficiency: 3.34 CoreMark/MHz*  and  1.25 / 1.50 / 1.89 DMIPS/MHz**

Arm Cortex-M3 Implementation Data***

180ULL
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 25°C)
Dynamic Power 141 µW/MHz 31 µW/MHz 11 µW/MHz
Floorplanned Area 0.35 mm2 0.09 mm2 0.02 mm2

  * see: http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1687&suite=CORE

  ** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

   *** Base usable configuration includes 1 IRQ + NMI, excludes ETM, MPU and debug


  • Manual containing technical information.
  • Cortex-M3 Technical Reference Manual

    For system designers, system integrators, verification engineers and software programmers who are building a Cortex-M3 based SoC.

    Read here
  • A program that is running on a desktop.
  • White Paper: Armv8-M Architecture

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • A guide on software optimization.
  • Cortex-M System Design Kit (CMSDK)

    CMSDK is a comprehensive system solution designed to work seamlessly with Cortex-M processors out-of-the-box.

    Learn more
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more

Get support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M3 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Suggested answer DWT 0 votes 57 views 1 replies Latest 23 hours ago by Joseph Yiu Answer this
Answered Armv7 Store Buffer 0 votes 215 views 6 replies Latest yesterday by Yang Wang Answer this
Suggested answer how dose the PC run to startup.s when the mcu reset
  • STM32 F7
0 votes 110 views 2 replies Latest yesterday by Joseph Yiu Answer this
Answered Digital design flow (synthesis) 0 votes 516 views 5 replies Latest yesterday by Joseph Yiu Answer this
Not answered AXI read response in error case 0 votes 48 views 0 replies Started yesterday by Anupam Jain Answer this
Answered A panic function to halt the processor in low-power sleep using WFI? 1 votes 233 views 5 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer DWT Latest 23 hours ago by Joseph Yiu 1 replies 57 views
Answered Armv7 Store Buffer Latest yesterday by Yang Wang 6 replies 215 views
Suggested answer how dose the PC run to startup.s when the mcu reset Latest yesterday by Joseph Yiu 2 replies 110 views
Answered Digital design flow (synthesis) Latest yesterday by Joseph Yiu 5 replies 516 views
Not answered AXI read response in error case Started yesterday by Anupam Jain 0 replies 48 views
Answered A panic function to halt the processor in low-power sleep using WFI? Latest yesterday by 42Bastian Schick 5 replies 233 views