Cortex-M3 Overview

The ARM Cortex-M3 processor is the industry-leading 32-bit processor for highly deterministic real-time applications, specifically developed to enable partners to develop high-performance low-cost platforms for a broad range of devices including microcontrollers, automotive body systems, industrial control systems and wireless networking and sensors. The processor delivers outstanding computational performance and exceptional system response to events while meeting the challenges of low dynamic and static power constraints. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area.

  • Cortex-M3 Technical Reference Manual

    For system designers, system integrators, verification engineers and software programmers who are building a Cortex-M3 based SoC.

    Technical Reference Manual
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Get the White Paper
  • Embedded Development Tools for Cortex-M Series

    ARM and its ecosystem partners provide a wide range of tools for embedded software development on ARM Cortex-M processors.

    Software Tools for Cortex-M
  • CMSDK
  • Cortex-M System Design Kit (CMSDK)

    CMSDK is a comprehensive system solution designed to work seamlessly with Cortex-M processors out-of-the-box. 

    Learn more about CMSDK

Highlights

Architecture

ARMv7-M Harvard

ISA Support Thumb® / Thumb-2
Pipeline 3-stage
Memory Protection Optional 8 region MPU with sub regions and background region
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt Controller Up to 240 Wake-up Interrupts
Sleep Modes Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with ARM Power Management Kit
Bit Manipulation Integrated Instructions & Bit Banding
Enhanced Instructions Hardware Divide (2-12 Cycles), Single-Cycle (32x32) Multiply, Saturated Math Support.
Debug Optional JTAG & Serial-Wire Debug Ports. Up to 8 Breakpoints and 4 Watchpoints.
Trace Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)

Key Features

Powerful debug and non-intrusive real-time trace

Comprehensive debug and trace features dramatically improve developer productivity. It is extremely efficient to develop embedded software with proper debug.

Memory Protection Unit (MPU)

Software reliability improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data.

Integrated nested vectored interrupt controller (NVIC)

There is no need for a standalone external interrupt controller. Interrupt handling is taken care of by the NVIC removing the complexity of managing interrupts manually via the processor.

Thumb-2 code density

On average, the mix between 16bit and 32bit instructions yields a better code density when compared to 8bit and 16bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory.

Characteristics

Performance Efficiency: 3.34 CoreMark/MHz*  and  1.25 / 1.50 / 1.89 DMIPS/MHz**

ARM Cortex-M3 Implementation Data***
180ULL
(7-track, typical 1.8v, 25°C)
90LP
(7-track, typical 1.2v, 25°C)
40LP
(9-track, typical 1.1v, 25°C)
Dynamic Power 141 µW/MHz 31 µW/MHz 11 µW/MHz
Floorplanned Area 0.35 mm2 0.09 mm2 0.02 mm2

  * see: http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1687&suite=CORE

  ** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone 

   *** Base usable configuration includes 1 IRQ + NMI, excludes ETM, MPU and debug