The Cortex-M3 processor is specifically developed to enable partners to develop high-performance low-cost platforms for a broad range of devices including microcontrollers, automotive body systems, industrial control systems and wireless networking and sensors.
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||Optional 8 region MPU with sub regions and background region|
|Interrupts||Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts|
|Interrupt Priority Levels||8 to 256 priority levels
|Wake-up Interrupt Controller
||Up to 240 Wake-up Interrupts|
||Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit
|Bit Manipulation||Integrated Instructions & Bit Banding
|Enhanced Instructions||Hardware Divide (2-12 Cycles), Single-Cycle (32x32) Multiply, Saturated Math Support
||Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.|
|Optional Instruction and Data Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)|
Powerful debug and non-intrusive real-time trace
Comprehensive debug and trace features dramatically improve developer productivity. It is extremely efficient to develop embedded software with proper debug.
Memory Protection Unit (MPU)
Software reliability improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data.
Integrated nested vectored interrupt controller (NVIC)
There is no need for a standalone external interrupt controller. Interrupt handling is taken care of by the NVIC removing the complexity of managing interrupts manually via the processor.
Thumb-2 code density
On average, the mix between 16bit and 32bit instructions yields a better code density when compared to 8bit and 16bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory.
Performance Efficiency: 3.34 CoreMark/MHz* and 1.25 / 1.50 / 1.89 DMIPS/MHz**
|Arm Cortex-M3 Implementation Data***|
(7-track, typical 1.8v, 25°C)
(7-track, typical 1.2v, 25°C)
(9-track, typical 1.1v, 25°C)
|Dynamic Power||141 µW/MHz||31 µW/MHz||11 µW/MHz|
|Floorplanned Area||0.35 mm2||0.09 mm2||0.02 mm2|
** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone
*** Base usable configuration includes 1 IRQ + NMI, excludes ETM, MPU and debug
Cortex-M3 Technical Reference Manual
For system designers, system integrators, verification engineers and software programmers who are building a Cortex-M3 based SoC.Read here
White Paper: Armv8-M Architecture
This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.Read here
Cortex-M System Design Kit (CMSDK)
CMSDK is a comprehensive system solution designed to work seamlessly with Cortex-M processors out-of-the-box.Learn more
Embedded Development Tools for Cortex-M Series
Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.Learn more
Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M3 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Arm Design Reviews Open a support case
The Cortex-M3 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes: