The ARM Cortex-M33 processor is the first feature rich implementation of the ARMv8-M architecture. The Cortex-M33 was developed to address all embedded and IoT markets especially those that require efficient security or digital signal control. TrustZone for ARMv8-M is the foundation of security for all embedded applications.
The processor has many optional features including DSP, a co-processor interface, memory protection units and a floating-point unit. The optional co-processor interface opens the door for customisation and extensibility to further decrease the power consumption of the system in the presence of frequent compute intensive operations. The Cortex-M33 achieves an optimal blend between real time determinism, energy efficiency, software productivity and system security which opens the door for many new applications and opportunities across diverse markets.
Cortex-M33 Technical Reference Manual - coming soon!For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M33 processor.
Embedded Development Tools for Cortex-M SeriesARM and its ecosystem partners provide a wide range of tools for embedded software development on ARM Cortex-M processors.
Software Tools for Cortex-M
White Paper: Cortex-M for beginners
This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.Get the White Paper
White Paper: ARMv8-M ArchitectureDownload this White Paper to get a technical overview of the ARMv8-M architecture and an introduction to TrustZone security technology.
Get the White Paper
|Architecture||ARMv8-M Mainline (Harvard)|
|ISA Support||Thumb® / Thumb-2|
|TrustZone||Optional TrustZone for ARMv8-M|
|Co-processor interface||Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute|
||Optional DSP/SIMD instructions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
|Floating Point Unit
||Optional single precision floating point unit
IEEE 754 compliant
||Optional Memory Protection Unit (MPU) with up to 16 regions per security state
||Non-maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels|
|Wake-up Interrupt Controller
||Optional for waking up the processor from state retention power gating or when all clocks are stopped
||Integrated wait for event (WFE) and wait for interrupt (WFI) instructions with Sleep On Exit functionality.
|Debug||Optional JTAG & Serial-Wire Debug Ports. Up to 8 Breakpoints and 4 Watchpoints.|
|Trace||Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM)|
TrustZone for ARMv8-M
A foundation for security for embedded devices. TrustZone offers software isolation to code, memory and I/O while retaining the requirements of embedded applications: real-time deterministic response, minimal switching overhead, and ease of software development.
Interested in learning how to program Secure and Non-secure domains on a processor with TrustZone?
A dedicated bus for extending the operation of the processor with tightly coupled co-processors to handle frequent and compute intensive operations in an ecosystem friendly manner. The interface supports up to eight accelerators and takes into account the security state of the co-processor.
SIMD, saturating arithmetic, fast MAC
Powerful instruction set for accelerating DSP applications, built right into the processor. A highly optimized DSP library built using these instructions is available free-of-charge from the ARM website (CMSIS Library).
Memory Protection Unit (MPU)
Software reliability and system security improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data. Each of the security zones can have a dedicated MPU that may be configured with a different number of regions.
Integrated Nested Vectored Interrupt Controller (NVIC)
There is no need for a standalone external interrupt controller. Interrupt handling is taken care of by the NVIC removing the complexity of managing interrupts manually via the processor.
Powerful debug and non-intrusive real-time trace
Comprehensive debug and trace features dramatically improve developer productivity. It is extremely efficient to develop embedded software with proper debug. It is extremely efficient and productive to develop embedded software with proper debug.
Performance efficiency 3.86 CoreMark/MHz* and 1.50 DMIPS**.
|ARM Cortex-M33 implementation data at 40LP (9-track, typical 1.1v, 25°C)|
|no TrustZone||with TrustZone|
|Dynamic Power||Please contact ARM||Please contact ARM
|Floorplanned Area||Please contact ARM||Please contact ARM
* Preliminary data
** Preliminary data, abides by all of the ground rules laid out in the Dhrystone documentation
Documents and blogs that will help users design ARM-based SoCs