The Arm Cortex-M33 processor is the first feature rich implementation of the Armv8-M architecture. 


The Cortex-M33 was developed to address all embedded and IoT markets especially those that require efficient security or digital signal control. TrustZone for Armv8-M is the foundation of security for all embedded applications. The processor has many optional features including DSP, a co-processor interface, memory protection units and a floating-point unit. The optional co-processor interface opens the door for customisation and extensibility to further decrease the power consumption of the system in the presence of frequent compute intensive operations. The Cortex-M33 achieves an optimal blend between real time determinism, energy efficiency, software productivity and system security which opens the door for many new applications and opportunities across diverse markets.

Everything you need to know about TrustZone for Armv8-M is here.

Block Diagram on Cortex-M33.

Key benefits

  • Provide a security foundation, offering isolation to protect valuable IP and data with TrustZone technology.

  • Extend the processor operation with the tightly coupled co-processor interface.

  • Simplify the design and software development of digital signal control systems with the integrated digital signal processing (DSP) instructions.

  • Accelerate single precision floating-point math operations up to 10x over the equivalent integer software library with the optional floating point-unit.

  • Achieve industry-leading system energy efficiency using the integrated software controlled sleep modes, extensive clock gating, and optional state retention.



Architecture Armv8-M Mainline (Harvard)
ISA Support Thumb/Thumb-2
Pipeline Three-stage
TrustZone Optional TrustZone for Armv8-M
DSP Extensions
Optional DSP/SIMD instructions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Floating Point Unit
Optional single precision floating point unit
IEEE 754 compliant
Co-processor interface   
Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute
Memory Protection
Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels
Wake-up Interrupt Controller
Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes
Integrated wait for event (WFE) and wait for interrupt (WFI) instructions with Sleep On Exit functionality.
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.


Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM).

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The Cortex-M33 processor has been specifically designed for high-performance low-cost devices across a broad range of embedded market segments with a focus on security including:

Audio processing


Smart home/enterprise/building/planet

Sensor fusion and wearables


Single processing such as power and motor control

Key features

TrustZone for Armv8-M

A foundation for security for embedded devices. TrustZone offers software isolation to code, memory and I/O while retaining the requirements of embedded applications: real-time deterministic response, minimal switching overhead, and ease of software development.

Interested in learning how to program Secure and Non-secure domains on a processor with TrustZone?

Everything you need to know about TrustZone for Armv8-M is here.

Co-processor interface

A dedicated bus for extending the operation of the processor with tightly coupled co-processors to handle frequent and compute intensive operations in an ecosystem friendly manner. The interface supports up to eight accelerators and takes into account the security state of the co-processor.

SIMD, saturating arithmetic, fast MAC

Powerful instruction set for accelerating DSP applications, built right into the processor.  A highly optimized DSP library built using these instructions is available free-of-charge from the Arm website (CMSIS Library).

Memory Protection Unit (MPU)

Software reliability and system security improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data. Each of the security zones can have a dedicated MPU that may be configured with a different number of regions.

Integrated Nested Vectored Interrupt Controller (NVIC)

There is no need for a standalone external interrupt controller. Interrupt handling is taken care of by the NVIC removing the complexity of managing interrupts manually via the processor.

Powerful debug and non-intrusive real-time trace

Comprehensive debug and trace features dramatically improve developer productivity. It is extremely efficient to develop embedded software with proper debug. It is extremely efficient and productive to develop embedded software with proper debug.


Performance efficiency 3.86 CoreMark/MHz* and 1.50 DMIPS**.

 Arm Cortex-M33 implementation data at 40LP (9-track, typical 1.1v, 25°C)
  No TrustZone
With TrustZone
Dynamic Power
Please contact Arm
Please contact Arm
Floorplanned Area
Please contact Arm Please contact Arm

 * Preliminary data.
** Preliminary data, abides by all of the ground rules laid out in the Dhrystone documentation.

Related IP

The Cortex-M33 processor can be incorporated into an SoC using a broad range of Arm technology, including System IP and Physical IP. It is fully supported by development tools from Arm and the world’s #1 embedded ecosystem. Related IP includes:


Compatible IP

Corelink SSE-200 Subsystem

CoreLink SIE-200

TrustZone CryptoCell-312

Cortex-M System Design Kit

AMBA System Controllers

Arm CoreLink CG092 AHB flash cache

CoreLink SDK-200 System Design Kit

DS-5 Development Studio

Arm Keil MDK software development tool

Arm Compiler

Cortex-M Prototyping System

Fast Models

TrustZone for Armv8-M

Cortex Microcontroller System Interface Standard

Arm Mbed Pelion Device Platform


Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M33 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses Arm Design Reviews

  • Manual containing technical information.
  • Cortex-M33 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M33 processor.

    Read here
  • Manual containing technical information.
  • Cortex-M33 Devices Generic User Guide

    For application and system-level software developers, the Devices Generic User Guide provides programming information for the Cortex‐M33 processor.

    Read here
  • A program that is running on a desktop.
  • White Paper: Armv8-M Architecture

    Download this White Paper to get a technical overview of the Armv8-M architecture and an introduction to TrustZone security technology.

    Read here
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more
  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here

  • Product due to be released to  market.
  • Arm Design Reviews

    Arm's on-site design review service gives licensees confidence that their Cortex-M33 CPU is implemented efficiently, to provide maximum system performance, with lowest risk and fastest time-to-market.

    Learn more
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  • Questions? Request more information

    Learn more about Cortex-M33, Arm’s  first feature rich implementation of the Armv8-M architecture. Contact us to speak with our technical team.

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