Cortex-M33

The Arm Cortex-M33 processor is the first feature-rich implementation of the Armv8-M architecture. 

Block Diagram on Cortex-M33.

Getting Started

The Cortex-M33 was developed to address all embedded and IoT markets especially those that require efficient security or digital signal control. TrustZone for Armv8-M is the foundation of security for all embedded applications. The processor has many optional features including DSP, a co-processor interface, memory protection units and a floating-point unit. The optional co-processor interface opens the door for customisation and extensibility to further decrease the power consumption of the system in the presence of frequent compute intensive operations. The Cortex-M33 achieves an optimal blend between real time determinism, energy efficiency, software productivity and system security which opens the door for many new applications and opportunities across diverse markets.

Everything you need to know about TrustZone for Armv8-M is here.

Key benefits

  • Provide a security foundation, offering isolation to protect valuable IP and data with TrustZone technology.


  • Extend the processor operation with the tightly coupled co-processor interface.


  • Simplify the design and software development of digital signal control systems with the integrated digital signal processing (DSP) instructions.


  • Accelerate single precision floating-point math operations up to 10x over the equivalent integer software library with the optional floating point-unit.


  • Achieve industry-leading system energy efficiency using the integrated software controlled sleep modes, extensive clock gating, and optional state retention.

Access Cortex-M33 on the Cloud

Prototype software for next generation IoT applications with the full Cortex-M33 feature set with DesignStart FPGA on Cloud.

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Specifications

Architecture Armv8-M Mainline (Harvard)
ISA Support Thumb/Thumb-2
Pipeline Three-stage
TrustZone Optional TrustZone for Armv8-M
DSP Extensions
Optional DSP/SIMD instructions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Floating Point Unit
Optional single precision floating point unit
IEEE 754 compliant
Co-processor interface   
Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute
Memory Protection
Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels
Wake-up Interrupt Controller
Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes
Integrated wait for event (WFE) and wait for interrupt (WFI) instructions with Sleep On Exit functionality.
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.

Trace

Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM).

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Characteristics

Performance efficiency 3.96 CoreMark/MHz* and 1.50 DMIPS**

 Arm Cortex-M33 - Minimum Configuration (CLN28HT, 9-track)
  No TrustZone
With TrustZone
Dynamic Power (µW/MHz)***
6.3 7.6
Floorplan Area (mm²)
0.014 0.017

*Compiler AC6.11

Compiler options: CFlag options = -fomit-frame-pointer -fno-common -Omax -mthumb --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfloat-abi=hard -mfpu=fp-armv8-sp-16 LFlag options = -Omax

**Abides by all of the ground rules laid out in the Dhrystone documentation

***Measured running Dhrystone benchmark


  • Manual containing technical information.
  • Cortex-M33 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M33 processor.

    Read here
  • Manual containing technical information.
  • Cortex-M33 Devices Generic User Guide

    For application and system-level software developers, the Devices Generic User Guide provides programming information for the Cortex‐M33 processor.

    Read here
  • A program that is running on a desktop.
  • White Paper: Armv8-M Architecture

    Download this White Paper to get a technical overview of the Armv8-M architecture and an introduction to TrustZone security technology.

    Read here
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more
  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M33 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-M33 processor can be incorporated into an SoC using a broad range of Arm technology, including System IP and Physical IP. It is fully supported by development tools from Arm and the world’s #1 embedded ecosystem. Related IP includes:

 

Compatible IP
Tools
Software

Corelink SSE-200 Subsystem

CoreLink SIE-200

TrustZone CryptoCell-312

Cortex-M System Design Kit

AMBA System Controllers

Arm CoreLink CG092 AHB flash cache

CoreLink SDK-200 System Design Kit

DS-5 Development Studio

Arm Keil MDK software development tool

Arm Compiler

Cortex-M Prototyping System

Fast Models

TrustZone for Armv8-M

Cortex Microcontroller System Interface Standard

Arm Mbed Pelion Device Platform

Community Blogs

Community Forums

Answered Non-secure peripheral with a secure interrupt handler 0 votes 137 views 5 replies Latest 6 hours ago by Joseph Yiu Answer this
Suggested answer HREADY when no activity on bus 0 votes 92 views 2 replies Latest 9 hours ago by Tushar Valu Answer this
Suggested answer Store operations where the cache line is already cached (ACE protocol)
  • AMBA 4
1 votes 119 views 1 replies Latest 4 days ago by a.surati Answer this
Answered Whether Armv7-A has a Write Buffer 0 votes 505 views 8 replies Latest 5 days ago by Yang Wang Answer this
Suggested answer Why AXI4 changed the definition of AxCACHE?
  • AXI4
0 votes 160 views 1 replies Latest 6 days ago by Colin Campbell Answer this
Suggested answer AXI read response in error case 0 votes 175 views 1 replies Latest 7 days ago by Colin Campbell Answer this
Answered Non-secure peripheral with a secure interrupt handler Latest 6 hours ago by Joseph Yiu 5 replies 137 views
Suggested answer HREADY when no activity on bus Latest 9 hours ago by Tushar Valu 2 replies 92 views
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest 4 days ago by a.surati 1 replies 119 views
Answered Whether Armv7-A has a Write Buffer Latest 5 days ago by Yang Wang 8 replies 505 views
Suggested answer Why AXI4 changed the definition of AxCACHE? Latest 6 days ago by Colin Campbell 1 replies 160 views
Suggested answer AXI read response in error case Latest 7 days ago by Colin Campbell 1 replies 175 views