Cortex-M4

The Arm Cortex-M4 processor is Arm’s high performance embedded processor. 

Block Diagram on Cortex-M4.

Getting Started

The Cortex-M4 processor is developed to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. The combination of high-efficiency signal processing functionality with the low-power, low cost and ease-of-use benefits of the Cortex-M family of processors is designed to satisfy the emerging category of flexible solutions specifically targeting the motor control, automotive, power management, embedded audio and industrial automation markets.


Specifications

Architecture Armv7E-M Harvard
ISA Support Thumb/Thumb-2
Pipeline 3-stage + branch speculation
DSP Extensions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Hardware Divide (2-12 Cycles)
Floating-Point Unit
Optional single precision floating point unit
IEEE 754 compliant
Memory Protection
Optional 8 region MPU with sub regions and background region
Interrupts Non-maskable Interrupt (NMI+ 1 to 240 physical interrupts
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt Controller
Up to 240 Wake-up Interrupts
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit
Bit Manipulation
Integrated Instructions & Bit Banding
Debug
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.

Trace

Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM).

Characteristics

Performance Efficiency: 3.40 CoreMark/MHz* and without FPU: 1.25 / 1.52 / 1.91 DMIPS/MHz**, With FPU: 1.27 / 1.55 / 1.95 DMIPS/MHz**

Arm Cortex-M4 Implementation Data***

180ULL
(7-track, typical 1.8v, 25C)
90LP
(7-track, typical 1.2v, 25C)
40LP
(9-track, typical 1.1v, 85C)
Dynamic Power 151 µW/MHz 32.82 µW/MHz 12.26 µW/MHz
Floor plan Area 0.44 mm2 0.119 mm2 0.028 mm2

 * see: http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1448&suite=CORE

 ** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone .

 *** Base usable configuration includes DSP extensions, 1 IRQ + NMI, excludes ETM, MPU, FPU  and debug.


  • Manual containing technical information.
  • Cortex-M4 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M4 processor.

    Read here
  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • A guide on software optimization.
  • Cortex-M System Design Kit (CMSDK)

    CMSDK is a comprehensive system solution designed to work seamlessly with Cortex-M processors out-of-the-box.

    Learn more
  • a ulink, a board, a desktop.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A17 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

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Answered Whether Armv7-A has a Write Buffer Latest 2 days ago by Yang Wang 8 replies 416 views
Suggested answer Why AXI4 changed the definition of AxCACHE? Latest 2 days ago by Colin Campbell 1 replies 127 views
Suggested answer AXI read response in error case Latest 3 days ago by Colin Campbell 1 replies 132 views
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