The ARM Cortex-M7 processor is the most recent and highest performance member of the energy-efficient Cortex-M processor family, and enables partners to build the most sophisticated variety of MCUs and embedded SoCs.
The Cortex-M7 has been designed to deliver a very high level of performance, while maintaining the excellent responsiveness and ease-of-use of the ARMv7-M architecture. Its industry leading high-performance and flexible system interfaces are ideal for a wide variety of application areas including automotive, industrial automation, medical devices, high-end audio, image and voice processing, sensor fusion, advanced motor control and in the deployment of the Internet of Things (IoT).
Cortex-M7 Technical Reference Manual
The complete reference manual for system development, verification and programming on Cortex-M7 based SoCs.Technical Reference Manual
White Paper: Cortex-M for beginners
This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.Get the White Paper
Embedded Development Tools for Cortex-M SeriesARM and its ecosystem partners provide a wide range of tools for embedded software development on ARM Cortex-M processors.
Software Tools for Cortex-M
|DSP Extensions||Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Hardware Divide (2-12 Cycles)
|Floating Point Unit||Single and double precision floating point unit
IEEE 754 compliant
|Pipeline||6-stage superscalar + branch prediction|
|Interconnect||64-bit AMBA4 AXI, AHB peripheral port (64MB to 512MB)|
|Instruction cache||0 to 64 kB, 2-way associative with optional ECC|
|Data cache||0 to 64 kB, 4-way associative with optional ECC|
|Instruction TCM||0 to 16 MB with optional ECC|
|Data TCM||0 to 16 MB with optional ECC|
|Memory Protection||Optional 8 or 16 region MPU with sub regions and background region|
|Interrupts||Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts|
|Interrupt Priority Levels||8 to 256 priority levels|
|Wake-up Interrupt Controller||Up to 240 Wake-up Interrupts|
|Sleep Modes||Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with ARM Power Management Kit
|Bit Manipulation||Integrated Instructions|
|Debug||Optional JTAG & Serial-Wire Debug Ports. Up to 8 Breakpoints and 4 Watchpoints.|
|Trace||Optional Instruction and Data Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)|
Optional instruction and data TCMs up to 16MB
Fast access to critical code and data via a dedicated bus. Increases responsiveness to critical events.
Harvard instruction cache and data cache on 64-bit AMBA 4 AXI interface
Optimises access to large external memories or slow peripherals, reducing latency. Instruction and data caches are optional and separately configurable from 4KB to 64KB.
SIMD, saturating arithmetic, fast MAC
Powerful instruction set for accelerating DSP applications, built right into the processor. A highly optimised DSP library built using these instructions is available free-of-charge from the ARM website.
Powerful debug and non-obtrusive real-time trace, with optional full data trace
Comprehensive debug and trace features dramatically improve developer productivity. It is extremely efficient to develop embedded software with proper debug.
Memory Protection Unit (MPU)
Software reliability improves when each module is allowed access only to areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data.
Integrated nested vectored interrupt controller (NVIC)
There is no need for a standalone external interrupt controller. Interrupt handling is taken care of by the NVIC removing the complexity of managing interrupts manually via the processor.
Performance Efficiency: 5 CoreMark/MHz* and 2.14 / 2.55 / 3.23 DMIPS/MHz**
|ARM Cortex-M7 Implementation Data***|
(9-track, typical 0.9v, 85°C)
* CoreMark 1.0 : IAR Embedded Workbench v7.30.1 --endian=little --cpu=Cortex-M7 -e -Ohs --use_c++_inline --no_size_constraints / Code in TCM - Data in TCM
** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone
*** Base usable configuration includes 1 IRQ + NMI, excludes ETM, MPU, FPU and debug