The Arm Cortex-M7 processor is the highest performance member of the energy-efficient Cortex-M processor family.

Getting Started

The Cortex-M7 enables partners to build the most sophisticated variety of MCUs and embedded SoCs. It has been designed to deliver a very high level of performance, while maintaining the excellent responsiveness and ease-of-use of the Armv7-M architecture. Its industry leading high-performance and flexible system interfaces are ideal for a wide variety of application areas including automotive, industrial automation, medical devices, high-end audio, image and voice processing, sensor fusion, advanced motor control and in the deployment of the Internet of Things (IoT).

Block Diagram on Cortex-7.

Key benefits

  • Highest performance Cortex-M processor delivering best in class integer, floating point and DSP performance.

  • Low-power processor design with extensive clock and power gating, customizable to minimize power consumption and high energy efficiency.

  • Flexible system and memory interfaces including AXI, AHB, caches and tightly-coupled memories.

  • Safety-critical requirement support, with features like error recovery through memory Error Correction Code (ECC), full data trace, and full safety documentation.

  • C friendly programmer’s model and 100% binary compatible with existing Cortex-M3 and Cortex-M4 processors.



Architecture Harvard
ISA Support Armv7-M
Pipeline 6-stage superscalar + branch prediction
DSP Extensions
Single cycle 16/32-bit MAC
Single cycle dual 16-bit MAC
8/16-bit SIMD arithmetic
Hardware Divide (2-12 Cycles)
Floating-Point Unit
Optional single and double precision floating point unit
IEEE 754 compliant
64-bit AMBA4 AXI, AHB peripheral port
Instruction cache
0 to 64 kB, 2-way associative with optional ECC
Data cache
0 to 64 kB, 4-way associative with optional ECC
Instruction TCM
0 to 16 MB with optional ECC
Data TCM
0 to 16 MB with optional ECC
Memory Protection
Optional 8 or 16 region MPU with sub regions and background region
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Priority Levels
8 to 256 priority levels
Wake-up Interrupt Controller
Up to 240 Wake-up Interrupts
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with Arm Power Management Kit
Integrated Instructions
Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints.


Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM)

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Machine Learning on Cortex-M


The Cortex-M7 processor's industry leading high-performance and flexible system interfaces are ideal for a wide variety of application areas.

Audio processing


Industrial automation

Sensor fusion

Image and video processing

Advanced motor control



Key features

Optional instruction and data TCMs up to 16MB

Fast access to critical code and data via a dedicated bus.  Increases responsiveness to critical events.

Harvard instruction cache and data cache on 64-bit AMBA 4 AXI interface

Optimises access to large external memories or slow peripherals, reducing latency. Instruction and data caches are optional and separately configurable from 4KB to 64KB.

SIMD, saturating arithmetic, fast MAC

Powerful instruction set for accelerating DSP applications, built right into the processor.  A highly optimised DSP library built using these instructions is available free-of-charge from the Arm website.

Powerful debug and non-obtrusive real-time trace, with optional full data trace

Comprehensive debug and trace features dramatically improve developer productivity. It is extremely efficient to develop embedded software with proper debug.

Memory Protection Unit (MPU)

Software reliability improves when each module is allowed access only to areas of memory required for it to operate.  This protection prevents unexpected access that may overwrite critical data.

Integrated nested vectored interrupt controller (NVIC)

There is no need for a standalone external interrupt controller.  Interrupt handling is taken care of by the NVIC removing the complexity of managing interrupts manually via the processor.


Performance Efficiency: 5 CoreMark/MHz* and 2.14 / 2.55 / 3.23 DMIPS/MHz**

Arm Cortex-M7 implementation data*** 
  28 HPM
(9-track, typical 0.9v, 85°C)
Dynamic Power
 33 µW/MHz
Floorplanned Area

* CoreMark 1.0 : IAR Embedded Workbench v7.30.1 --endian=little --cpu=Cortex-M7 -e -Ohs --use_c++_inline --no_size_constraints / Code in TCM - Data in TCM.

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.

*** Base usable configuration includes 1 IRQ + NMI, excludes ETM, MPU, FPU and debug.


Related IP

The Cortex-M7 processor is usually incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP includes:


Compatible IP

Cortex-M System Design Kit

Socrates System Builder

AMBA System Controllers

DS-5 Development Studio

Arm Keil MDK software development tool

Arm Cortex-M7 Software Development Support

Cortex-M Prototyping System

Cortex Microcontroller Software Interface Standard

Arm Mbed Pelion Device Management



Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-M7 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses Arm Design Reviews

  • Manual containing technical information.
  • Cortex-M7 Technical Reference Manual

    The complete reference manual for system development, verification and programming on Cortex-M7 based SoCs.

  • A program that is running on a desktop.
  • White Paper: Cortex-M for beginners

    This White Paper compares the features of various Cortex-M processors and describes how to select the right processor for the application.

    Read here
  • A guide on software optimization.
  • Embedded Development Tools for Cortex-M Series

    Arm and its ecosystem partners provide a wide range of tools for embedded software development on Arm Cortex-M processors.

    Learn more

  • Product due to be released to  market.
  • Arm Design Reviews

    Arm's on-site design review service gives licensees confidence that their Cortex-M7 CPU is implemented efficiently, to provide maximum system performance, with lowest risk and fastest time-to-market.

    Learn more
  • The top half of a human.
  • Questions? Request more information

    Learn more about Cortex-M7, Arm’s most recent and highest performance member of the energy-efficient Cortex-M processor family. Contact us to speak with our technical team.

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