SecurCore SC000

The Arm SecurCore SC000 processor is designed specifically for the highest-volume smartcard and embedded security applications. 

Getting Started

The SC000 combines the low power and low area from the Cortex-M0 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M0. Therefore, the Cortex-M0 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 2.33 CoreMark/MHz* and 0.87/1.02/1.27 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power
74 µW/MHz 11.2 µW/MHz 4.6µW/MHz
 Floorplan area
0.125 mm2
0.034 mm2 0.008 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC000 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Forums

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Suggested answer reference source code to verify the Cortex-R52
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0 votes 89 views 1 replies Latest 19 hours ago by Jorney Answer this
Not answered MPU and TrustZone Started 7 hours ago by Talk2Joseph 0 replies 14 views
Suggested answer Cortex A15 SCU Latest 8 hours ago by Christopher Tory 1 replies 265 views
Suggested answer WT it non cache able memory when it broadcast at transaction Latest 8 hours ago by Christopher Tory 1 replies 162 views
Not answered Understanding XDMAC on Cortex-M7 Started 8 hours ago by Paul Braman 0 replies 14 views
Not answered How can I debug two A53 cores in DS-5 tool Started 18 hours ago by DriverLike 0 replies 18 views
Suggested answer reference source code to verify the Cortex-R52 Latest 19 hours ago by Jorney 1 replies 89 views