Arm SecurCore SC300

The Arm SecurCore SC300 processor is designed specifically for high-performance smartcard and embedded security applications. 

Block Diagram on SecurCore SC300.

Getting Started

The SC300 combines the benefits of the industry standard Cortex-M3 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M3. Therefore, the Cortex-M3 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 3.34 CoreMark/MHz* and 1.25/1.50/1.89 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power

 162 µW/MHz

37 µW/MHz 13 µW/MHz 
 Floorplan area
0.40 mm2
 0.10 mm2  0.028 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC300 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Suggested answer Store operations where the cache line is already cached (ACE protocol)
  • AMBA 4
1 votes 100 views 1 replies Latest 3 days ago by a.surati Answer this
Answered Whether Armv7-A has a Write Buffer 0 votes 474 views 8 replies Latest 4 days ago by Yang Wang Answer this
Suggested answer Why AXI4 changed the definition of AxCACHE?
  • AXI4
0 votes 145 views 1 replies Latest 5 days ago by Colin Campbell Answer this
Suggested answer AXI read response in error case 0 votes 154 views 1 replies Latest 6 days ago by Colin Campbell Answer this
Answered dsb and dmb 0 votes 1103 views 11 replies Latest 6 days ago by digital_kevin Answer this
Suggested answer DWT 0 votes 139 views 1 replies Latest 7 days ago by Joseph Yiu Answer this
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest 3 days ago by a.surati 1 replies 100 views
Answered Whether Armv7-A has a Write Buffer Latest 4 days ago by Yang Wang 8 replies 474 views
Suggested answer Why AXI4 changed the definition of AxCACHE? Latest 5 days ago by Colin Campbell 1 replies 145 views
Suggested answer AXI read response in error case Latest 6 days ago by Colin Campbell 1 replies 154 views
Answered dsb and dmb Latest 6 days ago by digital_kevin 11 replies 1103 views
Suggested answer DWT Latest 7 days ago by Joseph Yiu 1 replies 139 views