Arm SecurCore SC300

The Arm SecurCore SC300 processor is designed specifically for high-performance smartcard and embedded security applications. 

Block Diagram on SecurCore SC300.

Getting Started

The SC300 combines the benefits of the industry standard Cortex-M3 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M3. Therefore, the Cortex-M3 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 3.34 CoreMark/MHz* and 1.25/1.50/1.89 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power

 162 µW/MHz

37 µW/MHz 13 µW/MHz 
 Floorplan area
0.40 mm2
 0.10 mm2  0.028 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC300 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Forums

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Suggested answer Cortex A15 SCU
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0 votes 17 views 0 replies Started 9 hours ago by Paul Braman Answer this
Not answered How can I debug two A53 cores in DS-5 tool 0 votes 19 views 0 replies Started 19 hours ago by DriverLike Answer this
Suggested answer reference source code to verify the Cortex-R52
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0 votes 90 views 1 replies Latest 19 hours ago by Jorney Answer this
Not answered MPU and TrustZone Started 8 hours ago by Talk2Joseph 0 replies 15 views
Suggested answer Cortex A15 SCU Latest 9 hours ago by Christopher Tory 1 replies 267 views
Suggested answer WT it non cache able memory when it broadcast at transaction Latest 9 hours ago by Christopher Tory 1 replies 165 views
Not answered Understanding XDMAC on Cortex-M7 Started 9 hours ago by Paul Braman 0 replies 17 views
Not answered How can I debug two A53 cores in DS-5 tool Started 19 hours ago by DriverLike 0 replies 19 views
Suggested answer reference source code to verify the Cortex-R52 Latest 19 hours ago by Jorney 1 replies 90 views