Arm Cortex-R Series Processors

Cortex-R series processors deliver fast and deterministic processing and high performance, while meeting challenging real-time constraints in a range of situations. They combine these features in a performance, power and area optimized package, making them the trusted choice in reliable systems demanding high error-resistance.

  • Debug of Cortex-R Series Devices

    Debug and trace of Cortex-R series processors can be carried out through DS-5 Development Studio, with options for high speed serial trace.

    Development Tools
  • Functional Safety in Cortex-R

    For IEC 61508 and ISO 26262, Arm provides a safety certified compiler, plus hardware features such as memory protection, EDC, dual-core lock-step and fault containment.

    Safety Certified Arm Compiler
  • Safety Standards in the Arm Ecosystem

    Learn more about functional safety in hardware and software from medical to automotive and IoT applications. This whitepaper aslo covers the Armv8-R architecture.

    Safety Standards Whitepaper

Comparing Cortex-R Series Processors

Arm Cortex-R4 Arm Cortex-R5 Arm Cortex-R7 Arm Cortex-R8  Arm Cortex-R52
1.67 / 2.01 / 2.45 DMIPS/MHz*
3.47 CoreMark/MHz**
1.67 / 2.01 / 2.45 DMIPS/MHz*
3.47 CoreMark/MHz***
2.50 / 2.90 / 3.77 DMIPS/MHz*
4.35 CoreMark/MHz****
2.50 / 2.90 / 3.77 DMIPS/MHz*
4.35 CoreMark/MHz****
2.16 DMIPS/MHz
4.35 CoreMarks/MHz
Lockstep configuration Lockstep configuration
Dual-core Asymmetric Multi-Processing (AMP) configuration
Lockstep configuration
Dual-core Asymmetric Multi-Processing (AMP) with QoS configuration
Dual core Symmetric Multi-Processing (SMP) configuration
Lockstep configuration 
Dual, triple or quad-core Asymmetric Multi-Processing (AMP) with QoS configuration
Dual, triple or quad-core Symmetric Multi-Processing (SMP) configuration
Lockstep configuration 
Dual, triple or quad-core Asymmetric Multi-Processing (AMP) with QoS configuration
Dual, triple or quad-core Symmetric Multi-Processing (SMP) configuration

Tightly Coupled Memory (TCM) Tightly Coupled Memory
Low Latency Peripheral Port 
Accelerator Coherency Port
Micro Snoop Control Unit (µSCU)
Tightly Coupled Memory
Low Latency Peripheral Port 
Accelerator Coherency Port
Snoop Control Unit (SCU)
Tightly Coupled Memory
Low Latency Peripheral Port
Accelerator Coherency Port
Snoop Control Unit (SCU)

Tightly Coupled Memory
Low Latency Peripheral Port
Flash Port
8-stage dual issue pipeline with instruction pre-fetch and branch prediction 8-stage dual issue pipeline with instruction pre-fetch and branch prediction 11-stage superscalar pipeline with out-of-order execution and register renaming and advanced dynamic and static branch prediction with instruction loop buffer 11-stage superscalar pipeline with out-of-order execution and register renaming and advanced dynamic and static branch prediction with instruction loop buffer
8-stage dual issue pipeline with instruction pre-fetch and branch prediction
I-Cache and D-Cache I-Cache and D-Cache I-Cache and D-Cache  I-Cache and D-Cache
I-Cache and D-Cache
Hardware divide, SIMD, DSP Hardware divide, SIMD, DSP Hardware divide, SIMD, DSP  Hardware divide, SIMD, DSP
Hardware divide, NEON
IEEE754 Double Precision FPU IEEE754 Double Precision FPU or optimized SP Floating Point Unit IEEE754 Double Precision FPU or optimized SP Floating Point Unit IEEE754 Double Precision FPU or optimized SP Floating Point Unit
IEEE754 Double Precision FPU or optimized SP Floating Point Unit
Memory Protection Unit (MPU) with 8 or 12 memory regions Memory Protection Unit (MPU) with 12 or 16 memory regions Memory Protection Unit (MPU) with 12 or 16 memory regions Memory Protection Unit (MPU) with 12, 16, 20 or 24 memory regions
Stage-1 Memory Protection Unit (MPU) with 0 or 16 memory regions
Stage-2 Memory Protection Unit (MPU) with 0 or 16 memory regions
ECC and Parity protection on L1 memories ECC and Parity protection on L1 memories and AXI bus ports ECC and Parity protection on L1 memories and AXI bus ports.
Error Management with error bank
ECC and Parity protection on L1 memories and AXI bus ports.
Error Management with error bank
ECC and Parity protection on L1 memories and AXI bus ports
Bus interconnect protection 
Vectored Interrupt Controller (VIC) Port or Generic Interrupt Controller (GIC) Vectored Interrupt Controller (VIC) or Generic Interrupt Controller (GIC) Integrated Generic Interrupt Controller (GIC) Integrated Generic Interrupt Controller (GIC)
Integrated Generic Interrupt Controller (GIC), 32-960 interrupts

* The first result abides by all of the 'ground rules' laid out in the Dhrystone documentation, the second permits inlining of functions (not just the permitted C string libraries) while the third additionally permits simultaneous multifile complilation. All are with the original (K&R) v2.1 of Dhrystone.

** CFLAGS ="--cpu cortex-r4 -O3 -Otime --fpu softvfp -Ono_inline -Ono_multifile --fpmode=fast --loop_optimization_level=2"

*** CFLAGS ="--cpu cortex-r5 -O3 -Otime --fpu softvfp -Ono_inline -Ono_multifile --fpmode=fast --loop_optimization_level=2"

**** CFLAGS ="--cpu cortex-r5f -O3 -Otime -Ono_inline -Ono_multifile --fpmode=fast --loop_optimization_level=2"

Cortex-R series processors are all binary compatible, enabling software reuse and a seamless progression from one Cortex-R processor to another as functionality and/or additional processing power is required.

11-stage superscalar pipeline with out-of-order execution and register renaming and advanced dynamic and static branch prediction with instruction loop buffer
Hardware divide, SIMD, DSP