Cortex-R4

The Arm Cortex-R4 processor is the smallest deeply embedded real-time processor based on the Armv7-R architecture.

Cortex-R4 Block Diagram.

Getting Started

The Cortex-R4 processor delivers high-performance, real-time responsiveness, reliability, and dependability with high error-resistance. It offers excellent energy efficiency and cost effectiveness for ASIC, ASSP, and MCU embedded applications.

Specifications

Architecture Armv7-R
Instruction Set Arm and Thumb-2. Supports DSP instructions optional Floating-Point Unit with single-precision.
Microarchitecture Eight-stage pipeline with instruction pre-fetch, branch prediction and selected dual-issue execution. Parallel execution paths for load-store, MAC, shift-ALU, divide and floating point. Binary compatibility with the Arm9 and Arm11 embedded processors.
Cache controllers Harvard memory architecture with optional integrated Instruction and Data cache controllers. Cache sizes are in-dependably configurable from 4 to 64 kB. Cache lines are either write-back or write-through.
Tightly-Coupled Memories Optional Tightly-Coupled Memory interfaces are used for highly deterministic or low-latency applications that may not respond well to caching ( e.g. instruction code for interrupt service routines and data that requires intense processing). One or two logical TCMs, A and B, can be used for any mix of code and data. TCM size can be up to 8 MB. TCM B has two physical ports, B0 and B1, for interleaving incoming DMA data streams.
Interrupt Interface Standard interrupt, IRQ, and non-maskable fast interrupt, FIQ and inputs are provided together with a VIC interrupt controller vector port. The GIC interrupt controller can also be used if more complex priority-based interrupt handling is required. The processor includes low-latency interrupt technology that allows long multi-cycle instructions to be interrupted and restarted. Lengthy memory accesses are also deferred in certain circumstances. Worst-case interrupt response can be as low as 20-cycles using the FIQ alone.
Memory Protection Unit (MPU) Optional MPU configures attributes for either twelve or sixteen regions, each with resolution down to 32 Bytes. Regions can overlap, and the highest numbered region has highest priority.
Floating-Point Unit (FPU) Optional FPU implements the Arm Vector Floating Point architecture VFPv3 with 16 double-precision registers, compliant with IEEE 754. The FPU performance is optimized for single-precision calculations and has (optional) full support for double precision. Operations include add, subtract, multiply, divide, multiply and accumulate, square root, conversions between fixed and floating-point, and floating-point constant instructions.
ECC Optional single-bit error correction and double-bit error detection for cache and/or TCM memories with ECC bits. Single-bit soft errors automatically corrected by the processor. ECC protection possible on all external interfaces.
Parity Optional support for parity bit error detection in caches and/or TCMs.
Master AXI bus 64-bit AMBA AXI bus master for Level-2 memory and peripheral access.
Slave AXI bus Optional 64-bit AMBA AXI bus slave port allows DMA masters to access the dual-port TCM B interface for high speed streaming of data in and out of the processor.
Dual-core A dual-core processor configuration implements a redundant Cortex-R4 CPU in lock step with offset clocks and comparison logic for fault tolerant/fault detecting dependable systems.

Configuration Synthesizable Verilog RTL with facility to configure options for synthesis.
Debug Debug Access Port is provided. Functionality can be extended with DK-R4.
Trace An interface suitable for connection to CoreSight Embedded Trace Macrocell ETM R4 is present.

Characteristics

Cortex-R4 Single Processor 28 nm HPM
Maximum clock frequency Above 1.4 GHz
Performance 1.68 / 2.03 / 2.45 DMIPS/MHz*
3.47 CoreMark/MHz**
Total area (Including Core+RAM+Routing) From 0.21 mm2
Efficiency From 62 DMIPS/mW

* The first result abides by all of the 'ground rules' laid out in the Dhrystone documentation, the second permits inlining of functions (not just the permitted C string libraries) while the third additionally permits simultaneous multifile compilation. All are with the original (K&R) v2.1 of Dhrystone.

** CFLAGS ="--endian=little --cpu=Cortex-R4 --fpu=None -Ohs --no_size_constraints"


  • Manual containing technical information.
  • Cortex-R4 Technical Reference Manual

    In-depth technical manual for system designers, verification engineers and programmers who are using or building a Cortex-R4 based SoC.

    Read here
  • A program that is running on a desktop.
  • Cortex-R Series Programmer's Guide

    For software developers working in assembly language or C, this covers everything necessary to program Cortex-R series devices.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-R Series

    DS-5 Development Studio and a range of 3rd party and open source tools support Cortex-R series software development.

    Learn more

Get Support

 

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-R4 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Suggested answer Store operations where the cache line is already cached (ACE protocol)
  • AMBA 4
1 votes 100 views 1 replies Latest 3 days ago by a.surati Answer this
Answered Whether Armv7-A has a Write Buffer 0 votes 474 views 8 replies Latest 4 days ago by Yang Wang Answer this
Suggested answer Why AXI4 changed the definition of AxCACHE?
  • AXI4
0 votes 145 views 1 replies Latest 5 days ago by Colin Campbell Answer this
Suggested answer AXI read response in error case 0 votes 152 views 1 replies Latest 5 days ago by Colin Campbell Answer this
Answered dsb and dmb 0 votes 1102 views 11 replies Latest 6 days ago by digital_kevin Answer this
Suggested answer DWT 0 votes 138 views 1 replies Latest 7 days ago by Joseph Yiu Answer this
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest 3 days ago by a.surati 1 replies 100 views
Answered Whether Armv7-A has a Write Buffer Latest 4 days ago by Yang Wang 8 replies 474 views
Suggested answer Why AXI4 changed the definition of AxCACHE? Latest 5 days ago by Colin Campbell 1 replies 145 views
Suggested answer AXI read response in error case Latest 5 days ago by Colin Campbell 1 replies 152 views
Answered dsb and dmb Latest 6 days ago by digital_kevin 11 replies 1102 views
Suggested answer DWT Latest 7 days ago by Joseph Yiu 1 replies 138 views