The Arm Cortex-R5 processor forms a simple migration path from the Cortex-R4 processor, and onwards to the higher performance Cortex-R8 and Cortex-R52 processors. The Cortex-R5 processor builds on the feature set of the Cortex-R4 with enhanced error management, extended functional safety, and SoC integration features for use in deeply embedded real-time and safety-critical systems.
|Instruction Set||Arm and Thumb-2. Supports DSP instructions optional Floating-Point Unit with single-precision.
|Microarchitecture||Eight-stage pipeline with instruction pre-fetch, branch prediction and selected dual-issue execution. Parallel execution paths for load-store, MAC, shift-ALU, divide and floating point. Binary compatibility with the Arm9, Arm11, Cortex-R4 and Cortex-R7 embedded processors.
|Cache controllers||Harvard memory architecture with optional integrated Instruction and Data cache controllers. Cache sizes are in-dependably configurable from 4 to 64KB. Cache lines are either write-back or write-through.
|Tightly-Coupled Memories||Optional Tightly-Coupled Memory interfaces are used for highly deterministic or low-latency applications that may not respond well to caching ( e.g. instruction code for interrupt service routines and data that requires intense processing). One or two logical TCMs, A and B, can be used for any mix of code and data. TCM size can be up to 8MB. TCM B has two physical ports, B0 and B1, for interleaving incoming DMA data streams.
|Interrupt Interface||Standard interrupt, IRQ, and non-maskable fast interrupt, FIQ, inputs are provided together with a VIC interrupt controller vector port. The GIC interrupt controller can also be used if more complex priority-based interrupt handling is required. The processor includes low-latency interrupt technology that allows long multi-cycle instructions to be interrupted and restarted. Lengthy memory accesses are also deferred in certain circumstances. LLPP is intended to provide non-blocking access to GIC registers.
|Memory Protection Unit (MPU)||Optional MPU configures attributes for either twelve or sixteen regions, each with resolution down to 32 Bytes. Regions can overlap, and the highest numbered region has highest priority.
|Floating-Point Unit (FPU)||Optional FPU implements the Arm Vector Floating Point architecture VFPv3 with 16 double-precision registers, compliant with IEEE754. The FPU performance is optimized for single-precision calculations and has (optional) full support for double precision. Operations include add, subtract, multiply, divide, multiply and accumulate, square root, conversions between fixed and floating-point, and floating-point constant instructions.
|ECC||Optional single-bit error correction and double-bit error detection for cache and/or TCM memories with ECC bits. Single-bit soft errors automatically corrected by the processor. ECC protection possible on all external interfaces.
|Parity||Optional support for parity bit error detection in caches and/or TCMs.
|Master AXI bus||64-bit AMBA AXI bus master for Level-2 memory and peripheral access.
|Slave AXI bus||Optional 64-bit AMBA AXI bus slave port allows DMA masters to access the dual-port TCM B interface for high speed streaming of data in and out of the processor.
|Low Latency Peripheral Port (LLPP)||A dedicated 32-bit AMBA (AXI and optional AHB) port to integrate latency-sensitive peripherals more tightly with the processor.
|Accelerator Coherency Port (ACP)||A 64-bit AXI slave port to enable for coherency between the processor(s) and external intelligent peripherals such as DMA controllers, Ethernet or Flexray interfaces.
|Dual-core||A dual-core processor configuration for either a redundant Cortex-R5 CPU in lock-step for fault tolerant/fault detecting dependable systems or dual cores running independently, each executing its own program with its own bus interfaces, interrupts, and so on.
|Debug||Debug Access Port is provided. Functionality can be extended with DK-R5.
|Trace||An interface suitable for connection to CoreSight Embedded Trace Macrocell ETM R5 is present.
Processor area, frequency and power consumption are highly dependent on process, libraries and optimizations. The table below estimates a typical single processor implementation of the Cortex-R5 processor on mainstream low-power process technology (28 nm HPM) with high-density, standard-performance cell libraries and 32KB instruction cache and 32KB data cache.
|Cortex-R5 Single Processor||28nm HPM|
|Maximum clock frequency||Above 1.4 GHz|
|Performance||1.67 / 2.02 / 2.45 DMIPS/MHz*
|Total area (Including Core+RAM+Routing)||From 0.21 mm2|
|Efficiency||From 62 DMIPS/mW|
* The first result abides by all of the 'ground rules' laid out in the Dhrystone documentation, the second permits inlining of functions (not just the permitted C string libraries) while the third additionally permits simultaneous multifile compilation. All are with the original (K&R) v2.1 of Dhrystone.
** CFLAGS ="--endian=little --cpu=Cortex-R5 --fpu=None -Ohs --no_size_constraints"
Cortex-R5 Technical Reference Manual
Technical information for system designers and verification engineers working on Cortex-R5 based systems.Read more
Cortex-R Series Programmer's Guide
For Software developers working in assembly language, this guide covers programming Cortex-R series devices.Get the guide
Development Tools for Cortex-R Series
DS-5 Development Studio and a range of 3rd party and open source tools support Cortex-R series software development.Learn more
Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-R5 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Arm Design Reviews Open a support case
The Cortex-R5 processor can be incorporated into a SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. It is fully supported by Arm development tools. Related IP and tools include:
|Suggested answer||Store operations where the cache line is already cached (ACE protocol)||1 votes||100 views||1 replies||Latest 3 days ago by a.surati||Answer this|
|Answered||Whether Armv7-A has a Write Buffer||0 votes||474 views||8 replies||Latest 4 days ago by Yang Wang||Answer this|
|Suggested answer||Why AXI4 changed the definition of AxCACHE?||0 votes||145 views||1 replies||Latest 5 days ago by Colin Campbell||Answer this|
|Suggested answer||AXI read response in error case||0 votes||154 views||1 replies||Latest 6 days ago by Colin Campbell||Answer this|
|Answered||dsb and dmb||0 votes||1103 views||11 replies||Latest 6 days ago by digital_kevin||Answer this|
|Suggested answer||DWT||0 votes||140 views||1 replies||Latest 7 days ago by Joseph Yiu||Answer this|
|Suggested answer||Store operations where the cache line is already cached (ACE protocol) Latest 3 days ago by a.surati||1 replies 100 views|
|Answered||Whether Armv7-A has a Write Buffer Latest 4 days ago by Yang Wang||8 replies 474 views|
|Suggested answer||Why AXI4 changed the definition of AxCACHE? Latest 5 days ago by Colin Campbell||1 replies 145 views|
|Suggested answer||AXI read response in error case Latest 6 days ago by Colin Campbell||1 replies 154 views|
|Answered||dsb and dmb Latest 6 days ago by digital_kevin||11 replies 1103 views|
|Suggested answer||DWT Latest 7 days ago by Joseph Yiu||1 replies 140 views|