Cortex-R5 Overview

The Cortex-R5 processor builds on the feature set of the Cortex-R4 with enhanced error management, extended functional safety and SoC integration features for use in deeply embedded real-time and safety-critical systems.

  • Cortex-R5 Technical Reference Manual

    Technical information for system designers and verification engineers working on Cortex-R5 based systems.

    Technical Reference Manual

Cortex-R5 Highlights

Architecture ARMv7-R
Instruction Set ARM and Thumb-2. Supports DSP instructions optional Floating-Point Unit with single-precision.
Microarchitecture Eight-stage pipeline with instruction pre-fetch, branch prediction and selected dual-issue execution. Parallel execution paths for load-store, MAC, shift-ALU, divide and floating point. Binary compatibility with the ARM9ARM11Cortex-R4 and Cortex-R7 embedded processors.
Cache controllers Harvard memory architecture with optional integrated Instruction and Data cache controllers. Cache sizes are in-dependably configurable from 4 to 64KB. Cache lines are either write-back or write-through
Tightly-Coupled Memories Optional Tightly-Coupled Memory interfaces are used for highly deterministic or low-latency applications that may not respond well to caching ( e.g. instruction code for interrupt service routines and data that requires intense processing). One or two logical TCMs, A and B, can be used for any mix of code and data. TCM size can be up to 8MB. TCM B has two physical ports, B0 and B1, for interleaving incoming DMA data streams.
Interrupt Interface Standard interrupt, IRQ, and non-maskable fast interrupt, FIQ, inputs are provided together with a VIC interrupt controller vector port. The GIC interrupt controller can also be used if more complex priority-based interrupt handling is required. The processor includes low-latency interrupt technology that allows long multi-cycle instructions to be interrupted and restarted. Lengthy memory accesses are also deferred in certain circumstances. LLPP is intended to provide non-blocking access to GIC registers.
Memory Protection Unit (MPU) Optional MPU configures attributes for either twelve or sixteen regions, each with resolution down to 32 Bytes. Regions can overlap, and the highest numbered region has highest priority.
Floating-Point Unit (FPU) Optional FPU implements the ARM Vector Floating Point architecture VFPv3 with 16 double-precision registers, compliant with IEEE754. The FPU performance is optimized for single-precision calculations and has (optional) full support for double precision. Operations include add, subtract, multiply, divide, multiply and accumulate, square root, conversions between fixed and floating-point, and floating-point constant instructions.
ECC Optional single-bit error correction and double-bit error detection for cache and/or TCM memories with ECC bits. Single-bit soft errors automatically corrected by the processor. ECC protection possible on all external interfaces.
Parity Optional support for parity bit error detection in caches and/or TCMs.
Master AXI bus 64-bit AMBA® AXI bus master for Level-2 memory and peripheral access.
Slave AXI bus Optional 64-bit AMBA AXI bus slave port allows DMA masters to access the dual-port TCM B interface for high speed streaming of data in and out of the processor.
Low Latency Peripheral Port (LLPP) A dedicated 32-bit AMBA (AXI and optional AHB) port to integrate latency-sensitive peripherals more tightly with the processor
Accelerator Coherency Port (ACP) A 64-bit AXI slave port to enable for coherency between the processor(s) and external intelligent peripherals such as DMA controllers, Ethernet or Flexray interfaces.
Dual-core A dual-core processor configuration for either a redundant Cortex-R5 CPU in lock-step for fault tolerant/fault detecting dependable systems or dual cores running independently, each executing its own program with its own bus interfaces, interrupts, and so on.
Debug Debug Access Port is provided. Functionality can be extended with DK-R5.
Trace An interface suitable for connection to CoreSight™ Embedded Trace Macrocell ETM R5 is present.

Key Features

Higher system performance  and Advanced system level integration features

Dual-core configurations which enable twice the performance with Accelerator Coherency Port (ACP) and Micro Snoop Control Unit (micro SCU) maintaining data cache coherency with DMA I/O for both cores.

Improved reliability and safety features

Low-Latency Peripheral Port (LLPP), enhanced Memory Protection Unit (MPU) and enhanced ECC support.

Lock-step configurations

Second core provides redundancy for safety critical applications.

Extended functional safety support

Safety Documentation simplifies the certification effort for standards such as ISO26262 and IEC 61508, and enables higher levels of certifications.


Processor area, frequency and power consumption are highly dependent on process, libraries and optimizations. The table below estimates a typical single processor implementation of the Cortex-R5 processor on mainstream low-power process technology (28 nm HPM) with high-density, standard-performance cell libraries and 32KB instruction cache and 32KB data cache.

Cortex-R5 Single Processor 28nm HPM
Maximum clock frequency Above 1.4 GHz
Performance 1.67 / 2.02 / 2.45 DMIPS/MHz*
3.47 CoreMark/MHz**
Total area (Including Core+RAM+Routing) From 0.21 mm2
Efficiency From 62 DMIPS/mW

* The first result abides by all of the 'ground rules' laid out in the Dhrystone documentation, the second permits inlining of functions (not just the permitted C string libraries) while the third additionally permits simultaneous multifile complilation. All are with the original (K&R) v2.1 of Dhrystone.

** CFLAGS ="--endian=little --cpu=Cortex-R5 --fpu=None -Ohs --no_size_constraints"