The Cortex-R52 processor meets the rising performance needs of advanced real-time embedded systems. As the first Armv8-R processor, Cortex-R52 introduces support for a hypervisor, simplifying software integration with robust separation to protect safety-critical code.
|Instruction Set||Arm and Thumb-2. Supports DSP instructions and a configurable Floating-Point Unit either with single-precision or double precision and Neon.
|Microarchitecture||8-stage pipeline with instruction pre-fetch, branch prediction, superscalar in order execution, parallel execution paths for load-store, MAC, shift-ALU, divide and floating-point. Also features a hardware divider and is binary compatible with the Arm9, Arm11, Cortex-R4, Cortex-R5, Cortex-R7 and Cortex-R8 embedded processors.
|Up to quad-core||Multi-processor configurations of up to 4 integer CPUs within a single cluster or 8 logical cores (in DCLS configuration).|
|Dual Core Lock Step (DCLS)||Redundant Cortex-R52 cores in lockstep for fault detection in dependable systems with optional Split/lock configuration to decouple checking core enabling independent execution.|
|Safety Package|| Licensable, extended safety package to simplify product safety implementation.
|Self Test Technology||High fault coverage through ‘Built In Self Test’ capabilities (BIST).|
|Software Test Libraries||Complementary libraries providing additional non-destructive run time fault coverage.|
|Cache controllers||Optional Harvard memory architecture with write through Instruction and Data cache. Cache sizes are independently configurable for 4K to 32K.|
|Tightly-Coupled Memories||Optional Tightly-Coupled Memory interfaces are for highly deterministic or low-latency applications that may not respond well to caching (e.g. instruction code for interrupt service routines and data that requires intense processing). Cortex-R52 supports up to 3 TCMs, each up to 1MB.
|Generic Interrupt Controller||Fully integrated Generic Interrupt Controller (GIC) supporting complex priority-based interrupt handling managing standard interrupt (IRQ), fast interrupt (FIQ) inputs.The processor includes low-latency interrupt technology that allows long multi-cycle instructions to be interrupted and restarted. Deferral of lengthy memory accesses occurs in certain circumstances. Configurable to support from 32 to 960 interrupts including Software Generated Interrupts which can be routed between multiple cores.
|Memory Protection Unit (MPU)||
Level 1 MPU always implemented with optional Level 2 MPU
Up to 24 region Level 1 MPU configures attributes for regions from 64 bytes upwards with resolution of 64 bytes.
Optional additional Level 2 MPU operating at EL2 also configures attributes for up to 24 regions with as little as 64 Byte resolution. All transactions executed at EL0/EL1 perform a look-up in both MPUs with the combined least permissive attributes taken. All transactions executed at EL2 perform a look-up in Level 2 MPU only.
|Floating-Point Unit (FPU)||There is support for two FPU options: either a single precision-only with 32 32-bit single precision registers or double precision in Advanced SIMD implementations with 32 64 bit or 16 128 bit double precision registers. The FPU performance is optimized for both single and double precision calculations. Operations include add, subtract, divide, multiply, multiply and accumulate, square root, conversions between fixed and floating-point, and floating-point constant instructions.
|Advanced SIMD (NEON)||Optionally implement when double precision floating point is included is the Advanced SIMD supporting integer or single precision results.|
|ECC||Single-bit error correction and double-bit error detection for cache and TCM memories. All bus interfaces using Error Correcting Code (ECC). Single-bit soft errors are automatically corrected by the processor. In addition, full and flexible support for managing hard errors.
|Master AMBA AXI bus||128-bit AMBA AXI-4 bus master for Level-2 memory and peripheral access, with ECC protection.
|Slave AXI bus||128-bit AMBA AXI-4 bus slave port allows DMA masters to access the TCMs for high speed streaming of data in and out of the processor, with ECC protection.
|Low Latency Peripheral Port (LLPP)||A shared dedicated 32-bit AMBA AXI port to integrate latency-sensitive peripherals more tightly with the processor, with ECC protection.
|Flash Interface Port||Per core dedicated 128-bit AMBA AXI port to integrate latency-sensitive Flash memory tightly to a specific core within the processor cluster, ECC protection configurable for either 128-bit or 64-bit chunk size.
|Bus Interconnect Protection||Optional additional protection to guard against errors in the interconnect switch fabric, and end to end transaction protection.|
|Debug||Debug Access Port is provided. Its functionality can be extended using CoreSight Debug and Trace.
|Trace||Cortex-R-52 includes a CoreSight Embedded Trace Module that can be configured per core or shared between the cores in the cluster.
Cortex-R52 Technical Reference ManualFor system designers and software engineers, the Cortex-R52 manual provides information on implementing and programming Cortex-R52 based devices.
Cortex-R Series Programmer's Guide
For Software developers working in assembly language, this guide covers programming Cortex-R series devices.Get the guide
Development Tools for Cortex-R Series
DS-5 Development Studio and a range of 3rd party and open source tools support Cortex-R series software development.Learn more
Armv8-R and Safety
ETAS explore the implementation of AUTOSAR safety features using the Cortex-R52.
Armv8-R and Safety
Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-R52 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Arm Design Reviews Open a support case
Documents and blogs that will help users design Arm-based SoCs
The Cortex-R52 processor can be incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP and tools include:
|Answered||Non-secure peripheral with a secure interrupt handler||0 votes||142 views||5 replies||Latest 6 hours ago by Joseph Yiu||Answer this|
|Suggested answer||HREADY when no activity on bus||0 votes||92 views||2 replies||Latest 9 hours ago by Tushar Valu||Answer this|
|Suggested answer||Store operations where the cache line is already cached (ACE protocol)||1 votes||119 views||1 replies||Latest 4 days ago by a.surati||Answer this|
|Answered||Whether Armv7-A has a Write Buffer||0 votes||505 views||8 replies||Latest 5 days ago by Yang Wang||Answer this|
|Suggested answer||Why AXI4 changed the definition of AxCACHE?||0 votes||160 views||1 replies||Latest 6 days ago by Colin Campbell||Answer this|
|Suggested answer||AXI read response in error case||0 votes||175 views||1 replies||Latest 7 days ago by Colin Campbell||Answer this|
|Answered||Non-secure peripheral with a secure interrupt handler Latest 6 hours ago by Joseph Yiu||5 replies 142 views|
|Suggested answer||HREADY when no activity on bus Latest 9 hours ago by Tushar Valu||2 replies 92 views|
|Suggested answer||Store operations where the cache line is already cached (ACE protocol) Latest 4 days ago by a.surati||1 replies 119 views|
|Answered||Whether Armv7-A has a Write Buffer Latest 5 days ago by Yang Wang||8 replies 505 views|
|Suggested answer||Why AXI4 changed the definition of AxCACHE? Latest 6 days ago by Colin Campbell||1 replies 160 views|
|Suggested answer||AXI read response in error case Latest 7 days ago by Colin Campbell||1 replies 175 views|