The Cortex-R8 processor delivers twice the performance of the Cortex-R7 processor.
|Instruction Set||Arm and Thumb-2. Supports DSP instructions and optional Floating-Point Unit with single-precision or double precision.
|Microarchitecture||11-stage pipeline with instruction pre-fetch, branch prediction, superscalar and out of order execution, register renaming, parallel execution paths for load-store, MAC, shift-ALU, divide and floating-point. Also features a hardware divider and is binary compatible with the Arm9, Arm11, Cortex-R4, Cortex-R5 and Cortex-R7 embedded processors.
|Cache controllers||Harvard memory architecture with optional integrated Instruction and Data cache controllers. Cache sizes configurable from 4 to 64KB. Cache lines are write-back.
|Tightly-Coupled Memories||Optional Tightly-Coupled Memory interfaces are for highly deterministic or low-latency applications that may not respond well to caching (e.g. instruction code for interrupt service routines and data that requires intense processing). Instruction and/or data TCMs. Each TCM can be up to 1MB.
|Interrupt Interface||Standard interrupt, IRQ, non-maskable fast interrupt, FIQ, inputs are provided together with a fully integrated Generic Interrupt Controller (GIC) supporting complex priority-based interrupt handling. The processor includes low-latency interrupt technology that allows long multi-cycle instructions to be interrupted and restarted. Deferral of lengthy memory accesses occurs in certain circumstances.
|Memory Protection Unit (MPU)||Optional MPU configures attributes for up to twenty-four regions. Regions can overlap, and the highest numbered region has highest priority.
|Floating-Point Unit (FPU)||Optional FPU implements the Arm Vector Floating Point architecture VFPv3 with 16 double-precision registers, compliant with IEEE754. There is support for two FPU options: either a single precision-only or both single and double precision. The FPU performance is optimized for both single and double precision calculations. Operations include add, subtract, multiply, divide, multiply and accumulate, square root, conversions between fixed and floating-point, and floating-point constant instructions.
|ECC||Optional single-bit error correction and two-bit error detection for cache and/or TCM memories and all bus interfaces using Error Correcting Code (ECC). Single-bit soft errors are automatically corrected by the processor. In addition, full and flexible support for managing hard errors.
|Master AMBA AXI bus||64-bit AMBA AXI bus master for Level-2 memory and peripheral access.
|Slave AXI bus||Optional 64-bit AMBA AXI bus slave port allows DMA masters to access the TCMs for high speed streaming of data in and out of the processor.
|Low Latency Peripheral Port (LLPP)||A shared dedicated 32-bit AMBA AXI port to integrate latency-sensitive peripherals more tightly with the processor.
|Fast Path Port (FPP)
||An optional per core dedicated 32-bit AMBA AXI port to integrate latency-sensitive peripherals tightly with a specific core within the processor.
|Accelerator Coherency Port (ACP)||A 64-bit AMBA AXI slave port to enable coherency between the processor(s) and external intelligent peripherals such as DMA controllers, companion DSPs, Ethernet or Flexray interfaces.
|Low latency memory port||A 64-bit AMBA AXI master port designed to connect to local memory. This local memory provides many of the benefits of TCM and in addition can be slower and lower power and also easily shared between the one, two, three or four Cortex-R8 processor cores.
|Up to quad-core||Coherent multi-processor configurations with the cores running independently, each executing its own program with its own bus interfaces(Asymetric Multiprocessor Mode) or with a single operating system managing the cores (Symertric Multiprocessor Mode).
|Dual Core Lock Step (DCLS)||Redundant Cortex-R8 cores in lock-step for fault tolerant/fault detecting dependable systems.
|Debug||Debug Access Port is provided. Its functionality can be extended using CoreSight SoC-400.
|Trace||Cortex-R8 includes a CoreSight Embedded Trace Module that can be configured per core or shared between the cores in the cluster.
Processor area, frequency and power consumption are highly dependent on process, libraries and optimizations. The table below estimates a typical single processor implementation of the Cortex-R8 processor on mainstream low-power process technology (28nm HPM) with high-density, standard-performance cell libraries and 32 KB instruction cache and 32 KB data cache.
|Cortex-R8 Single Processor||28 nm HPM|
|Maximum clock frequency||Above 1.5 Ghz|
|Performance||2.50 / 2.90 / 3.77 DMIPS/MHz *
|Total area (Including Core+RAM+Routing)||From 0.33 mm2
|Efficiency||From 46 DMIPS/mW|
* The first result abides by all of the 'ground rules' laid out in the Dhrystone documentation, the second permits inlining of functions (not just the permitted C string libraries) while the third additionally permits simultaneous multifile compilation. All are with the original (K&R) v2.1 of Dhrystone.
** CFLAGS ="--endian=little --cpu=Cortex-R8 --fpu=None -Ohs --no_size_constraints"
Cortex-R8 Technical Reference Manual
For system designers and software engineers, the Cortex-R8 manual provides information on implementing and programming Cortex-R8 based devices.
Cortex-R Series Programmer's Guide
For Software developers working in assembly language, this guide covers programming Cortex-R series devices.Get the guide
Development Tools for Cortex-R Series
DS-5 Development Studio and a range of 3rd party and open source tools support Cortex-R series software development.Cortex-R Tools
Arm training courses, including a course on upgrading from Cortex-R7, and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-R8 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Arm Design Reviews Open a support case
The Cortex-R8 processor can be incorporated into a SoC using a broad range of Arm technology including System IP and Physical IP. It is fully supported by Arm development tools. Related IP and tools include:
|Not answered||MPU and TrustZone||0 votes||14 views||0 replies||Started 7 hours ago by Talk2Joseph||Answer this|
|Suggested answer||Cortex A15 SCU||0 votes||266 views||1 replies||Latest 8 hours ago by Christopher Tory||Answer this|
|Suggested answer||WT it non cache able memory when it broadcast at transaction||0 votes||164 views||1 replies||Latest 8 hours ago by Christopher Tory||Answer this|
|Not answered||Understanding XDMAC on Cortex-M7||0 votes||16 views||0 replies||Started 9 hours ago by Paul Braman||Answer this|
|Not answered||How can I debug two A53 cores in DS-5 tool||0 votes||18 views||0 replies||Started 18 hours ago by DriverLike||Answer this|
|Suggested answer||reference source code to verify the Cortex-R52||0 votes||89 views||1 replies||Latest 19 hours ago by Jorney||Answer this|
|Not answered||MPU and TrustZone Started 7 hours ago by Talk2Joseph||0 replies 14 views|
|Suggested answer||Cortex A15 SCU Latest 8 hours ago by Christopher Tory||1 replies 266 views|
|Suggested answer||WT it non cache able memory when it broadcast at transaction Latest 8 hours ago by Christopher Tory||1 replies 164 views|
|Not answered||Understanding XDMAC on Cortex-M7 Started 9 hours ago by Paul Braman||0 replies 16 views|
|Not answered||How can I debug two A53 cores in DS-5 tool Started 18 hours ago by DriverLike||0 replies 18 views|
|Suggested answer||reference source code to verify the Cortex-R52 Latest 19 hours ago by Jorney||1 replies 89 views|