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Can Cortex-M3 measure the cycle count of its own activity?

Information in this article applies to:

  • Cortex-M3

  • Cortex-M4


Can Cortex-M3 measure the cycle count of its own activity?


If the DWT is implemented, the processor can measure elapsed cycles be reading the DWT_CYCCNT register at the start and end of the time interval of interest, and calculating the difference in value.

Alternatively, the processor can use its SysTick function to measure elapsed cycle counts.

The SysTick function must be configured to use the processor clock as the reference timing source. The count will be accurate up to a 24-bit maximum number of clock cycles from the point where the STCVR is re-loaded.

// Systick regs

int *STCSR = (int *)0xE000E010;

int *STRVR = (int *)0xE000E014;

int *STCVR = (int *)0xE000E018;

// Configure Systick

*STRVR = 0xFFFFFF; // max count

*STCVR = 0; // force a re-load of the counter value register

*STCSR = 5; // enable FCLK count without interrupt

The cycle count for an operation can then be obtained by reading the STCVR immediately before and immediately after the operation in question. As STCVR is a down counter, the number of core clock cycles taken by the operation is given by:

(STCVR1 - STCVR2 - 2)

The overhead of 2 cycles is because the read of the STCVR is Strongly Ordered with regard to other memory accesses or data processing instructions, although there is an exception to this general rule; two consecutive reads to the STCVR, without any intervening data processing or external memory access instrucitons, will pipeline and therefore show an overhead of only 1 cycle (ie. the STCVR values will show a difference of only 1).

Related information

Not applicable.

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