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How do I compile assembly code to support DSU system registers?

Article ID: 213555213

Published date: 06 Jun 2018

Last updated: -

Applies to: Compilers

Problem/Question

How do I compile assembly code to support DynamIQ Shared Unit (DSU) system registers?

Scenario

The GCC compiler fails to build assembly code in the following cases:

  • For some special environments, use an old GCC version to compile assembly code that contains the new Arm IP mnemonic register names, such as DynamIQ Shared Unit (DSU) CLUSTERPWRSTAT_EL1. However, the build fails because the old GCC version cannot recognize CLUSTERPWRSTAT_EL1.

  • In a special time window, the GCC latest version is still in development. Therefore, there is no GCC version that can support the latest mnemonic register names of new Arm IPs. The assembly code contains the new system register names of new Arm IPs, so the latest GCC fails to build the assembly code.

What can I do to support the new Arm IP mnemonic registers in these cases?

Answer

To support the new Arm IP mnemonic register names in compiling the assembly code, you must use the encoding names provided by the Technical Reference Manual (TRM) documents.

Consider the case of the DSU system register CLUSTERPWRSTAT_EL1 as an example. You can access the DSU system registers as the following example code:

mrs x0, S3_0_C15_C3_5 // CLUSTERPWRCTLR_EL1

mrs x0, S3_0_C15_C3_6 // CLUSTERPWRDN _EL1

mrs x0, S3_0_C15_C3_7 // CLUSTERPWRSTAT_EL1

The following table describes the details about the DSU system register

Register mnemonic

Op0

CRn

Op1

CRm

Op2

Width

CLUSTERPWRCTLR_EL1

3

C15

0

C3

5

32

CLUSTERPWRDN_EL1

3

C15

0

C3

6

32

CLUSTERPWRSTAT_EL1

3

C15

0

C3

7

32

Check Arm Architecture Reference Manual about the Reserved encodings for IMPLEMENTATION DEFINED registers section for details. For example:

Accessing the S3_<op1>_<Cn>_<Cm>_<op2>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax is encoded with the following settings in the instruction encoding:

  • <op1> is in the range 0 - 7.

  • <CRn> can take the values: 11, 15.

  • <CRm> is in the range 0 - 15.

  • <op2> is in the range 0 - 7.

The value of <Cn> must be either 11 or 15. Other values may refer to architecturally-defined registers.

Workaround

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Example

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Related Information

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