Unparalleled Insight into System Execution
Modern processors are complex. Multiple cores and clusters with cross triggering, a AMBA® system bus, DSP, secondary Cortex®-M series cores and custom IP blocks require a flexible approach to trace.
With synchronization between source code, trace capture, register and address values, ARM® DS-5 Development Studio trace viewer helps to give you an unparalleled insight into the inner workings of your SoC.
Instruction and Data Trace
Instruction trace enables the non-intrusive debug of random time-related issues, which are difficult to replicate by stepping through the code, and the performance analysis of critical areas of software. Data trace optionally records address and register values from load and store instructions. Combined with the instruction trace this gives a complete record of execution.
When trace is enabled, DS-5 begins to capture instructions and data. Trace can be downloaded from the trace buffer at any time, or once the capture is complete. Trace data is synchronized with the code view. DS-5 Professional Edition and DS-5 Ultimate Edition make it easy to configure trace for complex system topologies based around ARMv7 and ARMv8 respectively.
The Instrumentation Trace Macrocell (ITM) and System Trace Macrocell (STM) provide high-bandwidth, low latency “printf-style” instrumentation links. ITM and STM output is routed to the on-chip trace bus, and can be collected by the debugger and displayed in its Event Viewer or exported to a text file. Using the CoreSight Global Timestamp, trace from all these sources can be synchronized and cross referenced. Additionally, when using DSTREAM-ST, the ITM and STM trace data is live streamed to the host PC so that the DS-5 Debugger Events View can update and show the instrumentation trace data live from the target system.
Depending on the zoom level selected, the trace visualization shows either a heat map of instructions executed, or at 1:1 scale, a representation of memory accesses, branch instructions and other instructions in red, yellow and green respectively.
Using Tracepoints and Filters
By default, DS-5 traces everything executed by a processor into a circular buffer.
Trace start and trace stop points enable you to restrict trace to certain areas of the code. This is useful to optimize the analysis of certain functions when tracing to an ETB, or to prevent ETM FIFO overflows when the trace port is slow.
Ranges (also called filters) can be used in conjunction with trace start and trace stop points. They enable you to select an address range outside of which trace is always disabled.
Triggers are highlighted in the trace view and the tools can be configured to collect trace around, before, or after the trigger. Just check the ETM Triggers Halt Execution box in the debug configuration menu to trace around a trigger point.
Trace typically requires a JTAG connection to devices featuring an Embedded Trace Macrocell (ETM) or Program Trace Macrocell (PTM). Data trace is not available on all cores. The amount of trace recorded is limited by the size of the on-chip Embedded Trace Buffer (ETB). If you need a larger buffer; trace off-chip to the 4GB buffer in DSTREAM or live stream the trace to the host PC using DSTREAM-ST.
Setting up your target device for trace
DS-5 includes an abstraction layer, known as the debug and trace services layer (DTSL). This gives you an easy way to establish a JTAG debug connection and access the various CoreSight trace macrocells. By autodetecting the SoC topology via DSTREAM or DSTREAM-ST, device bring-up is made much quicker than it otherwise would be.
Configuring Trace in DS-5
Once trace elements for custom devices have been defined with a combination of autodetection and scripting, you will see the same configuration options that would be available for off-the-shelf devices.
From DS-5, you can turn on cycle-accurate trace, control which cores to collect trace from and set the trace capture range for the available trace sources. For custom devices and for situations where the memory map or location/amount of memory available to the Trace Memory Controller (TMC) change, we've made it possible to add extra tabs and controls for trace elements.
CoreSight On-Target Access Library & Snapshot Viewer
The CoreSight on-target access library enables the software running on your ARM target to interact directly with CoreSight devices, enabling “flight-recorder” trace. This removes the need to attach an external debugger, allowing you to debug software crashes in the field. DS-5 includes an example application to illustrate the use of the CoreSight library on a hardware target. The collected data can then be exported for use in DS-5 Debugger. Read our tutorial for using the CoreSight Access Library here.
For easy use of the CoreSight on-target access library, DS-5 Debugger contains DS-5 snapshot viewer, which enables you to open register values, memory values and debug symbols captured from software in the field. For instance, this allows you to analyze trace data collected during a crash dump.