DS-5 Example Code
Arm DS-5 Development Studio includes a large number of examples that show the development, debug and optimization of bare-metal (no operating system), RTOS and Linux-based systems. These include startup code and application examples for a range of Cortex-A, R and M processors. For RTOS-based systems, there are examples for both RTXv4 and RTXv5 application development and debug. For Linux developers, there are examples of Linux application debug (via gdbserver), Linux kernel and Linux kernel module debug. There are also examples that demonstrate Streamline and compiler optimization. For power users, there are examples of Jython scripting in the debugger, Debug and Trace Services Layer (DTSL) and the CoreSight Access Library. You'll also find bare-metal Hello World examples for a range of vendors development boards.
DS-5 examples are part of the DS-5 installation and are located in one or more archive files inside
<ds-5 installation directory>/examples directory. The Importing DS-5 examples tutorial shows how to import and run these sample code projects.
Bare-Metal Startup Code
DS-5 provides bare-metal (no operating system) startup code examples for a range of Cortex-A, Cortex-R and Cortex-M family of processors. The examples typically include assembler code for the vector table, exception handlers, cache/MMU or TCM/MPU initialization, and FPU/NEON initialization code, together with a simple application written in C. Multi-core SMP examples are also provided for Armv8-A targets. The examples can be compiled with Arm Compiler 5 and Arm Compiler 6, and run on FVP models or real hardware. Examples for Armv7 processors are located in the archive file
Bare-metal_examples_Armv7.zip, and for Armv8 processors are located in
Bare-Metal Application Debug
These examples show you how to use DS-5 Debugger to debug bare-metal applications, running on one or more cores, using the "Fireworks" or "Primes" example application. "Fireworks" produces a graphical simulated fireworks display. "Primes" can use one or more cores to find prime numbers, using shared memory and mutexes to arrange co-operation between multiple cores. Version of "Primes" that show the use of the Instrumentation Trace Macrocell (ITM) and System Trace Macrocell (STM) to transport information to DS-5 Debugger's Event Viewer are also provided. The examples can be compiled with Arm Compiler 5 and Arm Compiler 6, and run on FVP models or real hardware. Examples for Armv7 processors are located in the archive file
Bare-metal_examples_Armv7.zip, and for Armv8 processors are located in
Linux Application and Linux Kernel Debug
For Linux developers, DS-5 comes with examples to illustrate debugging Linux applications (via gdbserver), the Linux kernel and Linux kernel modules. The code for these examples is located in the archive file
The Linux application examples include:
- a simple "Hello World" written in C that illustrates building a console application for Arm Linux
- a "Threads" example to illustrate support for debug of multi-threaded Arm Linux applications, for Armv7-A and Armv8-A
- an example based on the "Gnometris" game that illustrates support for debug of a complex application that is written in C++, including shared libraries.
There is a tutorial that shows the debug of the Armv8-A Linaro Linux kernel, and the Linux kernel module example uses a simple character device driver written in C to illustrate the support for debug of Linux kernel modules.
Streamline is a Performance Analysis tool in DS-5 that enables you to analyze the performance of bare-metal systems, systems with a Real Time Operating System (RTOS), or systems based on Linux, Android and Tizen. These examples illustrate how to use Streamline to analyze system performance. The code for these examples is located in the archive file
- Performance analysis of Arm Linux Applications illustrates Streamline performance analysis, including annotation, using the example "Xaos" application.
- Streamline Cache Test example illustrates the use of Streamline to reveal cache efficiency by way of simple instrumented C code.
- Streamline Annotations example illustrates the use of Streamline annotations by way of simple instrumented C code.
Debugger Scripting with Jython
Jython is a Java implementation of the Python scripting language. It provides extensive support for data types, conditional execution, loops and organization of code into functions, classes and modules, as well as access to the standard Jython libraries. Jython is an ideal choice for larger or more complex scripts. DS-5 Debugger has a documented API that enables Jython scripts to utilize its target connection and control facilities. Example Jython scripts how how you can access registers, variables, memory, translations tables and the Performance Monitor Unit (PMU) on a target via DS-5 Debugger. These examples are located in the archive file
Debug and Trace Services Layer (DTSL)
The Debug and Trace Services Layer (DTSL) is a software layer that sits between DS-5 Debugger and the RDDI target access API. DS-5 Debugger uses DTSL to create target connections, configure the target platform to be ready for debug operations, and communicate with the debug components on the target. As a power user of DS-5 Debugger, you might need to use DTSL as part of new platform support, to extend the capabilities of DS-5 Debugger, to add support for custom debug components, or to create your own Java or Jython programs which interact with your target. Examples are provided that show how to access and control CoreSight components such as ELA-500, ELA-600, STM and trace capture and decode, located in the archive file
TrustZone is a feature of the Arm architecture that allows code to be partitioned into secure and non-secure compartments. These examples for Armv7-A and Armv8-M demonstrates the support for TrustZone in DS-5 Debugger, including how to debug separate secure and non-secure executables at source level. The code for these examples is located in the archive file
CoreSight Access Library
This example demonstrates CoreSight Access Library. The CoreSight Access Library API enables directly programmable access with CoreSight devices on your target. This allows, for example, program execution trace to be captured in a production system without the need to have an external debugger connected. The saved trace can be retrieved later and loaded into DS-5 Debugger for analysis.The library supports a number of different CoreSight components on several target boards as described in the readme.md file (part of the example). An example Linux application ("tracedemo") that exercises the library is provided. As it runs, tracedemo creates several files on the target, including the captured trace. Ready-made example capture files are provided that can be loaded into DS-5 Debugger. The code for the example is located in the archive file
Scalable Vector Extension (SVE)
These examples demonstrate the use of the Scalable Vector Extension (SVE) for Armv8-A. The code for the example is located in the archive file
Development Board Debug
Bare-metal software development examples illustrate compilation with the Arm Compiler 5 and bare-metal debug connection to supported boards. The code is located in the archive file
Bare-metal_boards_examples.zip. These examples show basic connection and debug illustrated by a simple bare-metal semihosted "hello world" example application loaded into on-chip RAM.
- Altera Arria 10 and Cyclone V SoCs
- Atmel AT91-series and ATSAMA5D35-EK
- BeagleBoard (including -xM)
- FDI LPC3250
- Icytecture i.MX35 Starter Board
- LOGIC PD OMAPL138, ZOOM AM1808 EVM, AM3517, i.MX27 LITEKIT, i.MX31 LITEKIT, OMAP34x-II MDP
- Mistral OMAP AM37x EVM
- NXP Vybrid VF6xx (Cortex-A5 and Cortex-M4), i.MX28 EVK, i.MX50 EVK, i.MX51 PDK, i.MX53 Quick Start Board, i.MX6Q
- ST SPEAr300, SPEAr310, SPEAr320, SPEAr600
- Samsung Exynos 4210, and S5PC100, S5PC110, S5PV210 SMDKs
- Silica Phytec i.MX35
- Spansion Traveo
- Spectrum Digital AM1707 EVM
- Xilinx Zynq 7000
- nVidia Tegra 250 developer kit