Corstone foundation IP diagram.

Arm Corstone-101 Foundation IP Overview

The Arm Corstone-101 foundation IP offers:

  • The fundamental system elements to design SoCs around Arm Cortex-M0/M0+/M3/M4 processor.
  • A starting point for building your next SoC for IoT and embedded applications.
  • The minimum level of security with a full TRNG.

The Corstone-101 foundation IP helps you to build SoC designs for your next Arm Cortex-M processor. It supersedes the popular Corstone-100 foundation IP, bringing together the contents of the Corstone-100 (including the subsystem and system IP), adding the latest Flash Controller IP from Arm. The Flash Controller IP, which Arm has named the Arm CoreLink GFC-100 Generic Flash Controller, is compliant with the AMBA Generic Flash Bus Protocol Specification and eases development of your next SoC for IoT and automotive applications.

Corstone-101 Foundation IP Technical Overview 

Get the overview of the functionality in the Corstone-101 foundation IP.

*Note that the Corstone-101 foundation IP was formerly named SDK-101.

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Benefits of the Arm Corstone-101 Foundation IP

A product being released to the market.

Save time and risk in your development by utilizing the fundamental elements.

Ability to automate items on a connection.

Leverage Arm expertise for IoT applications.

3 components linked together (Core Components).

Flexibility to differentiate. Utilize what components you need. Avail easy process migration!

Corstone-101 Components

  • CoreLink SSE-050 Subsystem – An excellent starting point, offering an expandable subsystem based on the Arm Cortex-M3 processor for IoT applications.
  • CMSDK – including many additional components, including the multi-layer AHB generator, bridges, adaptors and controllers, offering a reliable and efficient way to connect your system. The CMSDK package even features a few system examples to inspire your future design.
  • AHB Flash Cache – Flash-based systems (either with embedded Flash or external Flash) often heavily rely on an efficient cache system. The AHB Flash Cache block significantly improves performance and power consumption of your SoC within a compact area.
  • RTC – A real-time clock for applications that need to maintain a time base counter.
  • TRNG – Security needs to be implemented from the beginning. The True Random Number Generator is the fundamental security element to integrate in a device and provide the essential foundations of security from the start.
  • CoreLink GFC-100 – A generic flash Controller IP enabling process portability. It is also is in line with the AMBA Generic Flash Bus Protocol Specification

The Arm Corstone-101 foundation IP is a crucial toolkit for your next Arm Cortex-M based design, offering both software and hardware components. It offers the essential core elements needed in your next SoC design.

It helps to build reliable designs from the very beginning, meaning that SoC designers can now focus on differentiating their SoC designs, rather than the basic building blocks of system IP. It also gives you the flexibility to incorporate different non-volatile memory types and processes.


About CoreLink GFC-100

The main differentiator between Corstone-100 foundation IP and Corstone-101 foundation IP is the new Arm CoreLink GFC-100 Generic Flash Controller, offering easy migration from one foundry process technology to another. The CoreLink GFC-100 Generic Flash Controller contains the process-independent (or generic) part of a Flash Controller and applies for any non-volatile memory. By using this, partners do not need to modify their flash controllers for different foundry and process variants.


CoreLink GFC-100 is demonstrated as the Generic part along the GFB interface in the figure below.

A diagram to show CoreLink GFC-100

Partners can now concentrate on designing only the process-specific part of flash controller, thus focus on innovating their designs and differentiating their products. Partners also get the full flexibility to create their ‘process-dependent’ or ‘process-specific’ designs for a given foundry. Additionally, save time to get your products out to market and make them compliant to AMBA GFB!

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Not answered When Wrapping happens in AXI? Started 10 hours ago by hayk 0 replies 20 views
Not answered When should APB slave Sample address/Data for read/write transaction from APB master? Started 7 days ago by arm_user 0 replies 40 views
Not answered Timing simulation with ARM standard library Started 9 days ago by Yongchan Jeon 0 replies 41 views
Not answered Can the ARM corrupt the timing on the AXI bus Started 15 days ago by skbrown 0 replies 67 views
Suggested answer Cycle Model Studio software Latest 20 days ago by Jason Andrews 1 replies 213 views
Suggested answer why PSTRB signal in APB4 have four bits? Latest 1 months ago by Colin Campbell 2 replies 461 views