Cortex-M System Design Kit.


The Cortex-M System Design Kit includes:

  • A selection of AMBA AHB and APB infrastructure components
  • Essential peripherals such as GPIO, timers, watchdog, and UART
  • Example systems for Cortex-M0, Cortex-M3 and Cortex-M4 processors
  • Compilation and simulation scripts for the Verilog environment
  • Software drivers and example programs


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  • Cortex-M System Design Kit Technical Reference Manual

    The Technical Reference Manual is written for system designers to design products with the Arm Cortex-M processors.

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Cortex-M System Design Kit System Example

The Cortex-M System Design Kit provides example AMBA systems to bring the designer to a point of a working system as quickly as possible, offering a library of fundamental peripherals and interconnect generation along with software drivers and examples.

The example system supports a number of configuration options. For example:

  • DMA option – if the ARM CoreLink DMA-230 DMA controller is licensed you can plug in the DMA controller and use it in the system immediately. You can also modify the design to use your own DMA controller.
  • Bit band wrapper – if the system requires bit band compatibility with Cortex-M3 or Cortex-M4 this functionality can be included.
  • Boot ROM – this option demonstrates how to design a system with boot loader ROM in addition to the user program memory (for example Flash).

It is straightforward to extend the example system and plug in other peripheral designs. For designers new to AMBA, the example AHB and APB slaves are a good starting point for your design.

An example system for Cortex-M3 and Cortex-M4 processors is also included, as the following figure shows.

The Cortex-M3 or Cortex-M4 system has the same memory map and interrupt assignments as the Cortex-M0 system. It also uses the same AMBA APB subsystem as the Cortex-M0 example. Again, the integration of the DMA controller and boot loader are optional.


CMSDK Description

For embedded designs, the Cortex-M System Design Kit is a comprehensive set of IP that helps developers build SoCs for this application.

The Cortex-M System Design Kit consists of:

APB components

  • APB example slave.
  • APB timer.
  • APB dual timer.
  • APB watchdog.
  • APB slave multiplexer.
  • APB subsystem.
  • APB timeout monitor.


Advanced AHB-Lite components

  • AHB bus matrix.
  • AHB upsizer.
  • AHB downsizer.
  • AHB to APB asynchronous bridge.
  • AHB to AHB and APB asynchronous bridge.
  • AHB to AHB synchronous bridge.
  • AHB to AHB sync-down bridge.
  • AHB to AHB sync-up bridge.


The memory models

  • ROM model wrapper.
  • RAM model wrapper.
  • Behavioral SRAM model with AHB interface.
  • 32-bit Flash ROM behavioral model.
  • 16-bit Flash ROM behavioral model.
  • SRAM synthesizable (for FPGA) model.
  • External asynchronous 8-bit SRAM.
  • External asynchronous 16-bit SRAM.

The verification components

  • AHB-Lite protocol checker.
  • APB protocol checker.
  • AHBFile Reader Bus Master(FRBM).


Cortex-M System Design Kit Features

Modifiable system solution for Cortex-M0+, M0, M3 and M4

  • Optimized and designed to work out-of-box with Cortex-M processors
  • Optimized for low latency/power/area applications (e.g. mixed-signal)

Essential AMBA interconnects and peripherals

  • Comprehensive AHB and APB infrastructure support
  • Baseline peripherals UART, timers, GPIO, watchdog

Software support

  • Example programs for Keil MDK
  • DS-5 Professional, GCC
  • CMSIS header files & software driver

Verification components

  • AMBA protocol checkers, File Reader Bus Functional Models

Peripherals Overview

Low latency AHB/GPIO

  • 16-bit with masked access address ranges for bit accesses


  • 8-bit UART with transmit and receive interrupts
  • Overflow detect

Simple APB Timer

  • 32-bit down counter
  • external input as clock or clock enable

Dual Timer

  • 16-bit & 32-bit operations
  • Three operation modes

Watchdog timer

  • 32-bit operation, support NMI and reset generation

Example AHB and APB slaves

  • Easy to use starting point for peripheral migration