Getting Started

Fast Models are accurate, flexible programmer's view models of Arm IP, allowing you to develop software such as drivers, firmware, OS and applications prior to silicon availability. They allow full control over the simulation, including profiling, debug and trace. Fast Models can be exported to SystemC and TLM 2.0, allowing integration into the wider SoC design process.

A bug, A chip, a robot etc.

Components in a Virtual Prototype

A complete virtual prototype of a system contains more than just an Instruction Set Simulator. A full system consists of:

  • Fast, accurate models of cores, subsystems or systems
  • SystemC interface for integration with EDA tools and other IP blocks
  • APIs for debug (CADI) and trace (MTI), allowing full control and an interface to DS-5, MDK and 3rd party debug tools
  • Python based scripting for runtime control, checking and reporting
  • Visualization, file system access, peripherals and networking from virtual I/O
  • Fully compatible Linaro software stacks, from boot code to Linux and Android OS support

Software Development with Fast Models

Complete & Accurate

Fast Models are available for all Cortex processors, CCI and CCN interconnect, as well as other system IP. Fast Models are functionally accurate, so banked and co-processor registers, exception levels, translation tables and cache coherency are all available to programmers.

Hybrid Simulation

Connect a CPU subsystem to peripherals on hardware emulators via AMBA transactors for emulation acceleration. Compatible with Cadence, Mentor Graphics and Synopsys emulators for maximum flexibility in your software development and IP validation process.

Save and Restore

Checkpointing allows you to save your simulation once the OS has booted, so that you can restart from there and jump quickly back into your software. For regression testing, multiple simulations can be restarted from a single checkpoint.

Timing Annotation

Fast Models interact with TLM approximately timed models for high level software performance estimation. This helps to give an idea of how software will perform on the real device, saving software development time further into the project.

Fast Models Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Fast Models.

CPU Fast Models

CPU Family Processor
Cortex-A Series Cortex-A32, Cortex-A35, Cortex-A53, Cortex-A55, Cortex-A57, Cortex-A72, Cortex-A73, Cortex-A75, Cortex-A76 new, Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9, Cortex-A15, Cortex-A17
Cortex-R Series Cortex-R52, Cortex-R8, Cortex-R4, Cortex-R5, Cortex-R7
Cortex-M Series Cortex-M23, Cortex-M33, Cortex-M35P new, Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4, Cortex-M7

Fixed Virtual Platform Downloads

Fixed versions of Fast Models are also available, giving software developers a ready-to-use model of a complete Arm system. They can be downloaded, licensed individually and imported into DS-5 for ease of use. Fixed Virtual Platforms are a convenient way of testing software without needing to wait for development boards to become available.

Learn more


System IP Fast Models

System IP Family
Interconnect CCI-400, CCI-500, CCI-550, CCN-502, CCN-504, CCN-508, CCN-512, CMN-600
Interrupt Controllers GIC-400, GIC-500, GIC-600
System Memory Management Units MMU-400, MMU-500, MMU-600
Other DMC-620, DMC-500, DMC-520, DMC-400, DMA-330, TZC-400 

Peripherals and Infrastructure

Type Variant
Interfaces Ethernet, MMC, CLDC, HDLCD, VirtIO Block, Virtio Plan, VFS
Peripheral UART, MMU, Mouse and Keyboard, SSP, Timers, Clocks, GPIO
Memories RAM, Flash, NAND Flash, PL080, PL340, PL350, L2C-310
 TrustZone TZIC, TZMA, TZPC
Other Visualization, Bridges to AMBA-PV, PV Bus, File/App Loaders

Media IP Fast Models

 Media IP
 
 Mali Display Processors
 Mali-DP500, Mali-DP550, Mali-DP650, Mali-D71
 Mali Video Processors
 Mali-V550, Mali-V61
 Mali GPU
 Mali-G51, Mali-G71, Mali-G72, Generic Graphics Accelerator (GGA)


Architectural Fast Models

  Available Models
CPU
 Armv8-A (up to version 8.4), Armv8-M
 Interrupt Controller
 GICv2, GICv3
 SMMU  SMMUv3


Community Blogs

Community Forums

Not answered When should APB slave Sample address/Data for read/write transaction from APB master? 0 votes 27 views 0 replies Started 2 days ago by arm_user Answer this
Not answered Timing simulation with ARM standard library 0 votes 29 views 0 replies Started 4 days ago by Yongchan Jeon Answer this
Not answered Can the ARM corrupt the timing on the AXI bus
  • SoC FPGA
  • Timing & Addressing
0 votes 51 views 0 replies Started 9 days ago by skbrown Answer this
Suggested answer Cycle Model Studio software
  • Cycle Model Studio
0 votes 170 views 1 replies Latest 15 days ago by Jason Andrews Answer this
Suggested answer why PSTRB signal in APB4 have four bits?
  • AMBA 4
0 votes 422 views 2 replies Latest 1 months ago by Colin Campbell Answer this
Not answered [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! 0 votes 175 views 0 replies Started 1 months ago by jaycekr Answer this
Suggested answer apb protocol checker (assertions) 0 votes 492 views 1 replies Latest 1 months ago by Colin Campbell Answer this
Suggested answer Any advice on running 180nm ROM/RAM compilers on modern Linux? 0 votes 968 views 2 replies Latest 2 months ago by yrpeng Answer this
Suggested answer apb 2.0 continuous transfer 0 votes 474 views 1 replies Latest 2 months ago by Colin Campbell Answer this
Suggested answer AMBA AXI reset 0 votes 542 views 1 replies Latest 2 months ago by Colin Campbell Answer this
Not answered Coresight 400 tool installation and IP generation 0 votes 240 views 0 replies Started 3 months ago by PKB Answer this
Not answered CHI/ ACE-Lite Interface 0 votes 417 views 0 replies Started 3 months ago by Sidhaarth Answer this
Not answered When should APB slave Sample address/Data for read/write transaction from APB master? Started 2 days ago by arm_user 0 replies 27 views
Not answered Timing simulation with ARM standard library Started 4 days ago by Yongchan Jeon 0 replies 29 views
Not answered Can the ARM corrupt the timing on the AXI bus Started 9 days ago by skbrown 0 replies 51 views
Suggested answer Cycle Model Studio software Latest 15 days ago by Jason Andrews 1 replies 170 views
Suggested answer why PSTRB signal in APB4 have four bits? Latest 1 months ago by Colin Campbell 2 replies 422 views
Not answered [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! Started 1 months ago by jaycekr 0 replies 175 views
Suggested answer apb protocol checker (assertions) Latest 1 months ago by Colin Campbell 1 replies 492 views
Suggested answer Any advice on running 180nm ROM/RAM compilers on modern Linux? Latest 2 months ago by yrpeng 2 replies 968 views
Suggested answer apb 2.0 continuous transfer Latest 2 months ago by Colin Campbell 1 replies 474 views
Suggested answer AMBA AXI reset Latest 2 months ago by Colin Campbell 1 replies 542 views
Not answered Coresight 400 tool installation and IP generation Started 3 months ago by PKB 0 replies 240 views
Not answered CHI/ ACE-Lite Interface Started 3 months ago by Sidhaarth 0 replies 417 views