Complete & Accurate
Fast Models are available for all Cortex processors, CCI and CCN interconnect, as well as other system IP. Fast Models are functionally accurate, so banked and co-processor registers, exception levels, translation tables and cache coherency are all available to programmers.
Connect a CPU subsystem to peripherals on hardware emulators via AMBA transactors for emulation acceleration. Compatible with Cadence, Mentor Graphics and Synopsys emulators for maximum flexibility in your software development and IP validation process.
Save and Restore
Checkpointing allows you to save your simulation once the OS has booted, so that you can restart from there and jump quickly back into your software. For regression testing, multiple simulations can be restarted from a single checkpoint.
Fast Models interact with TLM approximately timed models for high level software performance estimation. This helps to give an idea of how software will perform on the real device, saving software development time further into the project.