CoreLink SSE-100 subsystem example diagram
The CoreLink SSE-100 subsystem contains the foundation IP necessary in most IoT endpoints. Pre-validated using the same methodology and processes that are used to ensure the quality of ARM IP, it reduces the design risk and accelerates SoC development projects for IoT nodes.
This AHB-lite multilayer crossbar interconnect links the system's main components. It features expansion ports to plug external master or slave components.
The integrated APB bridge also enables rapid connection of additional peripherals.
This controller attaches a configurable amount of SRAM to the system. It supports several instances of SRAM to precisely tune which ones can be powered-down or placed in retention mode.
With embedded Flash on chip, it is necessary to include caching in the system to minimize power consumption. The Flash cache allows a reduction of up to 99% of the number of Flash accesses.
This takes care of reducing the power consumption of the system to make sure that IoT devices built with this subsystem draw less current.